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- Newsgroups: comp.arch
- Path: sparky!uunet!haven.umd.edu!darwin.sura.net!bogus.sura.net!pandora.pix.com!stripes
- From: stripes@pix.com (Josh Osborne)
- Subject: Multi threaded CPUs
- Message-ID: <BtxHG0.8rz@pix.com>
- Summary: Where can I find out more about them?
- Sender: news@pix.com (The News Subsystem)
- Nntp-Posting-Host: pandora.pix.com
- Organization: Pix Technologies -- The company with no adult supervision
- References: <1811llINN3ci@usenet.INS.CWRU.Edu> <BtxGvn.8MH@pix.com>
- Date: Wed, 2 Sep 1992 01:57:35 GMT
- Lines: 14
-
- A little while ago I read about a RISC CPU (SPARC I think) that some
- researchers had designed. It had a cache of threads (I got the impresion
- that that includes registers, and posabble MMU state as well), four in
- the current chip, and when there was a pipe stall the execution would just
- switch to another thread.
-
- Unfortinutally the EE Design mag I read this in didn't say where to find out
- more, does anyone know anything about this?
- --
- stripes@pix.com "Security for Unix is like
- Josh_Osborne@Real_World,The Multitasking for MS-DOS"
- "The dyslexic porgramer" - Kevin Lockwood
- We all agree on the necessity of compromise. We just can't agree on
- when it's necessary to compromise. - Larry Wall
-