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- Newsgroups: comp.arch
- Path: sparky!uunet!stanford.edu!snorkelwacker.mit.edu!bloom-picayune.mit.edu!athena.mit.edu!jfc
- From: jfc@athena.mit.edu (John F Carr)
- Subject: Re: trapping speculative ops
- Message-ID: <1992Aug28.013846.11326@athena.mit.edu>
- Sender: news@athena.mit.edu (News system)
- Nntp-Posting-Host: achates.mit.edu
- Organization: Massachusetts Institute of Technology
- References: <BtEzrK.Jso.2@cs.cmu.edu> <GLEW.92Aug25180333@pdx007.intel.com> <BtLD9x.IBA@mentor.cc.purdue.edu>
- Date: Fri, 28 Aug 1992 01:38:46 GMT
- Lines: 14
-
-
- If the objective is to avoid branches, why not use a method for which
- precedent exists: add conditional operations to the architecture like HP and
- DEC have done. For memory, add non-trapping cache prefetch instructions as
- well as conditional loads and stores.
-
- A trap flag on each register is an interesting idea, but I think a greater
- performance increase can come from conditional operations. The hardware
- implementation may choose to use something like a trap flag, especially if
- it executes out of order, but making this invisible and implementation-
- dependent makes the hardware and software simpler.
-
- --
- John Carr (jfc@athena.mit.edu)
-