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- Path: sparky!uunet!cs.utexas.edu!torn!news.ccs.queensu.ca!qucdn!leek
- Organization: Queen's University at Kingston
- Date: Wednesday, 12 Aug 1992 14:18:39 EDT
- From: <LEEK@QUCDN.QueensU.CA>
- Message-ID: <92225.141839LEEK@QUCDN.QueensU.CA>
- Newsgroups: sci.electronics
- Subject: Re: 3.3 Volts
- References: <-+4m4y_.rudi@netcom.com>
- Lines: 33
-
- In article <-+4m4y_.rudi@netcom.com>, rudi@netcom.com (Rudolf Usselmann) says:
- >
- >Actually it started of with people trying to integrate more and more
- >smaller and smaller transistors on a very small die (i.e. 16mb DRAMS).
-
- At that size, the electric field associated with the higher +5V might
- becomes high. When the field strength gets too high, breakdown and
- other things might happened.
-
- >The two main advantages that you get by reducing the Voltage is that you
- >can use smaller tarnsistors and that you can increase the speed (3volt swing
- >The second reason is why the whole industry started to follow this trend.
- Power consumptions of devices are further reduced at low voltage. This
- is especially useful in low power applications. At lower voltages, less
- power goes into charging/discharging capacitive loads & also lowers the
- current when both P & N MOS are briefly switched on during transitions
- from one logic state to another.
-
- >Now this lower voltage is also used for "between chips" comunication
- >for the same reasons.
-
- Since CMOS input threshold is usually (*) 1/3 & 2/3 of power supply.
- At 3.3V, VL (Max) = 1V and VH(min) = 2V which is very comparable to
- that of standard TTL families. It simplifies things a lot that way.
- The near 0 or 3.3V outputs also keep TTL happy.
-
- (*) Yes CMOS can be made into TTL compatible (eg. HCT, ACT), but there
- are extra transistors involved.
-
- >rudi
-
- K. C. Lee
- Elec. Eng. Grad. Student
-