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- Newsgroups: comp.lsi.cad
- Path: sparky!uunet!haven.umd.edu!darwin.sura.net!jvnc.net!nuscc!nusunix2.nus.sg!eleleetk
- From: eleleetk@nusunix2.nus.sg (Mr Lee Teng Kiat)
- Subject: Example circuits for iSPLICE3
- Message-ID: <1992Aug15.015455.16779@nuscc.nus.sg>
- Sender: usenet@nuscc.nus.sg
- Reply-To: eleleetk@nusunix2.nus.sg
- Organization: Dept. of EE, National Univ. of Singapore
- Date: Sat, 15 Aug 1992 01:54:55 GMT
- Lines: 24
-
-
- Hello again, I just wonder if anyone of you out there has relatively
- *big* example circuits to test the mixed-mode capability of iSPLICE3.
- I am particularly interested in getting the circuits (static RAM,
- PLL, and ADC) mentioned the book 'Mixed-mode simulation' by Prof Saleh
- and Prof Newton.
-
- iSPLICE3 has implementations of MOS level 1 and 3 models but not the
- level 2. Could this be a reason for the very much improved simulation
- time even when full electrical simulation is done on some of the
- example circuits?
-
- Thanks for any help.
-
- Regards
-
- ----------------
- Teng-Kiat Lee VLSI CAD & Design Lab
- Internet: eleleetk@nusunix2.nus.sg Microelectronics Div.
- Bitnet: eleleetk@nusvm.bitnet or Dept. of Electrical Engineering
- ltk@nuseev.bitnet National University of Singapore
- Voice: (065)-772-6319 10 Kent Ridge Crescent
- (065)-467-1518 Singapore 0511
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-