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- Path: sparky!uunet!paladin.american.edu!darwin.sura.net!jvnc.net!yale.edu!qt.cs.utexas.edu!cs.utexas.edu!tamsun.tamu.edu!eemips.tamu.edu!kuttanna
- From: kuttanna@eemips.tamu.edu (Belliappa Kuttanna)
- Subject: Simulating processor architectures
- Message-ID: <1992Aug12.202438.11504@tamsun.tamu.edu>
- Sender: news@tamsun.tamu.edu (Read News)
- Organization: Texas A&M University
- Date: Wed, 12 Aug 1992 20:24:38 GMT
- Lines: 26
-
- Having developed a behavioral model of a processor, I want to measure
- its performance using some of the standard C benchmarks. In order to
- do this, a flow which starts with a C program & ends up producing
- a text file containing the instructions in either binary
- or hex formats, is required. Obviously, I need a compiler which uses
- the instruction set identical to the one used in the model.
- I have used the DLX instruction set (Hennessy - Patterson) since
- the gnu CC compiler can generate code using this instruction set.
- However, I do not know how to generate the Verilog input from the
- a.out or the assembly code file, without having to develop some
- software specifically for this purpose.
-
- If anyone has tried to use Verilog along these lines, PLEASE let me
- know how to proceed. Even if you have not, any ideas/comments on how
- to get around this problem are welcome. If you think that this flow
- will not work, please let me know.
- In addition, is there any other format in which the input file can be
- specified ?
-
- Any help in this regard will be greatly appreciated.
-
- Belliappa Kuttanna kuttanna@ee.tamu.edu
- Dept. of Electrical Engg.
- Texas A&M University.
-
-
-