NetNews Usenet Archive 1992 #18/NN_1992_18.iso/spool/comp/arch/8976

Text File | 1992-08-20 | 3.2 KB | 61 lines

Newsgroups: comp.arch
Path: sparky!uunet!usc!sol.ctr.columbia.edu!ira.uka.de!rz.uni-karlsruhe.de!usenet
From: [e-mail] (|S| Norbert Juffa)
Subject: Re: CACHE MISS PENALTY FOR 386/486??
In-Reply-To: [e-mail]'s message of Wed, 19 Aug 1992 04: 23:18 GMT
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Organization: University of Karlsruhe (FRG) - Informatik Rechnerabt.
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Date: Thu, 20 Aug 1992 16:58:58 GMT
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In <[e-mail]> [e-mail] writes:

> Just what is a typical cache miss penalty on
> (1) a 386 system with external cache
> (2) a 486 system with only internal cache
> (3) a 486 system with internal cache and external secondary cache
>
> I'm assuming an typical AT style system.
>
> Just how do you determine the miss penalty anyway?

The German computer magazine c't had a review of several identical configured
386 motherboards recently, each with a different chip set. They measured the
cache miss penalty for the cache controllers that are included in the chip set.
The cache miss penalty ranged between 3 clock cycles for an ACT chip set, 4
clock cycles for the Forex chip set up to 40 (for an UMC chip set, I think).
Apart from the speed of the cache logic, the cache line length heavily
influences time for a cache miss. Most 386 systems have 4 byte cache lines
that can be filled by a single access to memory. There are some that feature
longer cache lines, though. I think line sizes of up to 16 bytes are common.
In a naive approach, the CPU would have to wait until the complete cache line
had been loaded. There is a more clever approach possible that delivers the
word the CPU wanted directly to the CPU and fills the cache line afterwards
(I think this is called "read-around" or similar).

You should find data about the cache miss penalty for the 486 in the i486
Hardware Reference Manual available from Intel's literature department.

As for measuring the miss penalty, you try to force cache misses and measure
the load time from memory and then compare it to the time it takes the
memory access to complete in the case of 100% cache hits. Assume you have an
8 kByte cache. If you load a block of memory of exactly 8 kByte and read it
twice, you will have close to 100% hit rate on the second access (since the
386/486 feature unified code/data caches, executing the instructions to
read from memory throws out some of the data read before, but not much).
Now assume you read a 16 kByte block linearly into the same cache. After
the first read, the second 8 kByte half of the 16 kByte block will completely
occupy the cache. Now you read the same 16 kByte block again. On every access
to a cache line for the first 8 KByte, you have a cache miss. If you measure
the for both read operations and factor in the cache line length, you can
compute the miss time. I have tried this approach and it seems to work
quite well. There may be more sophisticated ideas though I am not aware of.


Norbert
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Norbert Juffa     email: [e-mail]          Live and let live!