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- Newsgroups: comp.arch
- Path: sparky!uunet!netnews!john
- From: john@netnews.jhuapl.edu (John Hayes)
- Subject: Caches and Hashing
- Message-ID: <Bt5DKp.z0@netnews.jhuapl.edu>
- Keywords: risc caches
- Organization: Applied Physics Laboratory of Johns Hopkins University
- Date: Mon, 17 Aug 1992 21:41:13 GMT
- Lines: 31
-
- There was an interesting idea in a recent article in Microprocessor
- Report. The article was describing HP's PA-RISC. Here is what caught
- my eye:
- "The caches are direct mapped to eliminate the performance
- impact of multiplexers that would be required with set-
- associativity. To reduce the cache miss rates, the addresses
- are hashed before they drive the cache SRAMS."*
-
- This raises several questions in my mind:
- 1) How much does hashing improve the miss rate of a direct-mapped
- cache?
- 2) The argument for direct mapped caches is that they have a better
- effective access time than set-associative caches because direct
- mapped caches do not need multiplexers to select the data. Would
- the cost of hashing eliminate this advantage? In other words:
- would a direct mapped cache with hashing or a set-associative
- cache (with associated multiplexers) give the best performance?
- 3) What hash function does HP use?
-
- I would be interestered to hear from anyone who knows the answer
- to these questions from papers or first-hand knowledge. I will
- summarize to the net.
-
- * Case, Brian, "HP Reveals Superscalar PA-RISC Implementation",
- Microprocessor Report, Vol. 6, No. 4, March 25, 1992, p. 17.
-
- -----------------------------------------------------------------
- John R. Hayes
- Applied Physics Laboratory
- Johns Hopkins University
- john@hecate.jhuapl.edu -or- john@aplcomm.jhuapl.edu
-