home *** CD-ROM | disk | FTP | other *** search
/ Liren Large Software Subsidy 15 / 15.iso / s / s205 / 1.ddi / BACKUP.001 / EXAMPLES_RMOORE.PDS < prev    next >
Encoding:
PALASM Design Description  |  1991-02-27  |  2.3 KB  |  73 lines
  1. ;-------------------------------------------------------------------;
  2. ;   To compare registered Mealy and registered Moore behavior:      ;
  3. ;-------------------------------------------------------------------;
  4. ;   Compile, simulate, and disassemble the files RMOORE.PDS and     ;
  5. ;   RMEALY.PDS. Compare simulation results and disassembled         ;
  6. ;   equations.                                                      ;
  7. ;-------------------------------------------------------------------;
  8.  
  9. ;PALASM Design Description
  10.  
  11. ;---------------------------------- Declaration Segment ------------
  12. TITLE    RMOORE.PDS
  13. PATTERN  A
  14. REVISION 1.0
  15. AUTHOR   FRANK J. LACOMBE
  16. COMPANY  KNOWLEDGE TREE SYSTEMS for AMD
  17. DATE     03/01/90
  18.  
  19. CHIP   REG_MOORE   PAL22V10
  20.  
  21. ;---------------------------------- PIN Declarations ---------------
  22. PIN  1          CLOCK                COMBINATORIAL             ; INPUT
  23. PIN  2          INA                  COMBINATORIAL             ; INPUT
  24. PIN  12         GND
  25. PIN  14         OUT1                 REGISTERED                ; OUTPUT
  26. PIN  15         OUT2                 REGISTERED                ; OUTPUT
  27. PIN  16         BITA                 REGISTERED                ; OUTPUT
  28. PIN  17         BITB                 REGISTERED                ; OUTPUT
  29. PIN  24         VCC
  30.  
  31. ;-----------------------------------State Segment ------------------
  32. STATE
  33. MOORE_MACHINE
  34. START_UP := POWER_UP -> STATE0              ;NOTE NEW START-UP STATE
  35.  
  36. STATE0 = /BITA * /BITB
  37. STATE1 = /BITA *  BITB
  38. STATE2 =  BITA * /BITB
  39. STATE3 =  BITA *  BITB
  40.  
  41. ;TRANSITION EQUATIONS------------------
  42. STATE0    :=  GO         -> STATE1
  43.           +->               STATE2
  44. STATE1    :=  GO         -> STATE2
  45.           +->               STATE3
  46. STATE2    :=  GO         -> STATE3
  47.           +->               STATE0
  48. STATE3    :=  GO         -> STATE0
  49.           +->               STATE1
  50.  
  51. ;OUTPUT EQUATIONS----------------------
  52. STATE0.OUTF    =  /OUT1 * /OUT2
  53. STATE1.OUTF    =  /OUT1 *  OUT2
  54. STATE2.OUTF    =   OUT1 * /OUT2
  55. STATE3.OUTF    =   OUT1 *  OUT2
  56.  
  57. CONDITIONS
  58. GO = INA
  59.  
  60. ;----------------------------------- Simulation Segment ------------
  61.  
  62. SIMULATION
  63. SETF INA
  64. CLOCKF CLOCK
  65. CLOCKF CLOCK
  66. CLOCKF CLOCK
  67. CLOCKF CLOCK
  68. SETF /INA
  69. CLOCKF CLOCK
  70. CLOCKF CLOCK
  71. CLOCKF CLOCK
  72. CLOCKF CLOCK
  73.