The CIA World Factbook 1992/k3bimage.iso/sel/04/0060/wstate.thd

Text File | 1991-12-02 | 13.9 KB | 233 lines

@* Which setup results in a faster system: running at 8 MHz with no wait
states, or at 10 MHz with one wait state?  Some benchmark results show that the
latter has a slight edge, despite theoretical arguments that would support the
opposite; and comparisons of 6 MHz/0 wait state machines with 8 MHz/1 wait
state systems bears out this effect.
This discussion took place on the IBMHW Forum of IBMNET on Compuserve; messages
edited by Joan Friedman 76556,3643.
@* Message no. range: 34204-35936
@* Date range: December 13-26, 1986
@* THE THEORY
Fm: Pete Holsberg 70240,334 13-Dec-86
To: DaveH 76054,171
Someone told me that there was an explanation of why an AT running at 10MHz
with 1-wait state is faster/slower than one that runs at 8MHz, no wait states.
Other than throughput, is there some other reason to prefer one over the other?
Fm: Dave Hoagland 76054,171 14-Dec-86
To: Pete Holsberg 70240,334
One major consideration in a "fast" machine is the ability of peripheral cards
to support the speed of the I/O bus.  In both cases (8mhz, zero wait state and
10mhz, one wait state) I would expect very few peripherals to have a problem.
If the two CPUs are running at those speeds (one wait state for the 10mhz
unit), I would expect the 8mhz, zero wait state machine to be faster (note that
its I/O bus will be running faster, too).  I've noticed that in most cpu
intensive operations, my XT286 (6mhz, zero wait state) is faster than my AT
(8mhz, one wait state), as one might expect.  As long as the combined clock
rate plus wait state or the "high speed" system results in slower operation
than the slower clock speed zero wait state setup, I'd pick the latter...but in
either case, the I/O compatibility should be considered.
I really think AST is approaching the situation quite intelligently in their
Premium 286.  The CPU is running at 10mhz, zero wait state, while a wait state
is introduced in their I/O bus.  This permits the use of standard peripherals.
However, there are two "Hot slots" (I think they refer to them as "fast slots")
that have a third connector.  These slots are available for cards specifically
designed to run at 10mhz, zero wait state (such as their FastRAM cards).  The
third connector provides a "direct pipeline" to the 80286.  I believe a
standard card can be plugged in the same slot, however, and since it doesn't
access the third connector, it will run normally with the standard I/O bus wait
state.
Fm: Doug Hogarth [PowerSoft] 76703,374 14-Dec-86
To: Pete Holsberg 70240,334 (X)
Although there are other considerations, my information is that each wait state
adds 25% slowdown.  I think that means the 10Mhz-1 wait would be more like a
7.5Mhz-0 wait, which is slower than an 8Mhz-0 wait.  Please don't depend on
that information, I could be wrong.
Fm: Pete Holsberg 70240,334 14-Dec-86
To: Dave Hoagland 76054,171 (X)
Hmmm.  Here's what I was thinking.  Please point out where the flaws are, OK?
Perhaps it's in my assumption that the '286, like the '86, has a 4 T-state bus
cycle.  If it does, then a bus cycle at 8MHz takes 4 * ( 1/8) = 500 ns, and 400
ns at 10 MHz. A wait state is 1 T-state in length, so at 10 MHz, a wait state
lasts 100 ns.  Thus at 10 MHz with 1 wait state, a bus cycle takes 400 + 100 ns
= 500 ns, exactly the same as 8MHz, no wait states. ???
Fm: Doug Hogarth [PowerSoft] 76703,374 14-Dec-86
To: Pete Holsberg 70240,334
I think it is more like the minimum bus cycle at 8Mhz-0 wait is 250ns, and at
10Mhz-1 wait is 300ns.  Those figures are overly pessimistic because the
pipelining within the 286 sometimes causes idel bus cycles while executing
prefetched instructions (that is from Intel literature).  The benchmark
difference works out to around 1/2 of the calculated difference.
Fm: Pete Holsberg 70240,334 14-Dec-86
To: Doug Hogarth [PowerSoft] 76703,374
If a bus cycle is four T-states and a T-state is a clock period, then an 8MHz
clock => 125ns periods, so four of them would be 500ns.  Is a '286 bus cycle
different from 4 T-states??  Gee, I wish I had Intel literature to read!!
Fm: Doug Hogarth [PowerSoft] 76703,374 14-Dec-86
To: Pete Holsberg 70240,334
Sorry, I don't have that info.  Perhaps it means something to you if I say that
the 286 has a double-frequency system clock.  The info I gave you about minimum
bus cycle time was from 4-3 of Intel's 286 Hardware Reference Manual.
Fm: Stephen Satchell 72736,70 15-Dec-86
To: Pete Holsberg 70240,334
The Intel 80286 uses two T states instead of four.  IBM places one wait T-state
into each cycle, unless the expansion board requests (a) no wait states or (b)
additional wait states.
Fm: Pete Holsberg 70240,334 16-Dec-86
To: Stephen Satchell 72736,70
When you say "IBM places one wait state..." you're talking about the 8MHz AT?
Is that for "main" memory or just expansion boards?
Lemme think...if we have 2 T-states per bus cycle, then a cycle at 8MHz is
250ns with 0 WSs, and a cycle at 10MHz is 200ns with no WSs and 300ns with 1
WS. So the 10MHz- 1WS is considerably slower than the 8MHz- 0WS.
Now if I go back and reread all those PC benchmarks, I ought to see some sense
there!
Fm: Stephen Satchell 72736,70 17-Dec-86
To: Pete Holsberg 70240,334
The information I put out is for the 6 MHz machine, but according to some
things I've read here and there, the AT 339 is 8 MHz 1 wait state.  BTW with
all the systems I've evaluated for Infoworld, I can verify with benchmark
numbers your statement that 10 MHz 1 ws is indeed slower than 8 MHz 0 ws.  You
would need a 12 MHz 1 ws machine to equal the RAM performance of a 8 MHz 0 ws
machine.  Some clever engineering could probably produce a 10 MHz 0.5 ws
machine, which would be a tad faster. [The 0.5 ws would be statistical, not a
reality!]
Fm: Pete Holsberg 70240,334 17-Dec-86
To: Stephen Satchell 72736,70 (X)
According to my lightning-swift calculation, a 12MHz - 1ws machine would
perform a bus cycle in 250ns, same as an 8MHz 0ws jobber!!  So, it looks like
an 8+0 is a better buy.  (?)
Fm: Steve Wallace 76010,2162 17-Dec-86
To: Stephen Satchell 72736,70
How about your views regarding speed, wait states, and memory chip speeds to
retain compatibility?
Fm: Stephen Satchell 72736,70 17-Dec-86
To: Steve Wallace 76010,2162 (X)
The principal problem with retaining compatibility on faster machines is to
insure that the I/O slots don't see any excessive super-speed that exceeds the
design guidelines.  So for an 8 MHz zero wait state machine I would be tempted
to insert two wait states at the I/O slot unless otherwise instructed by the
card.  For 10 MHz and faster machines, I would be tempted to divorce the chip
bus from the I/O bus, and use the standard Intel bus arbiter chips to resolve
any conflicts.  The I/O bus would run 6 and/or 8 MHz 1 wait state.  Access to
memory would be such that DMA, for example, would be buffered, and a cycle
stolen as required without slowing down high speed RAM.
This is not uncommon with non-desktop computer systems built on Multibus, by
the way.  Each board runs as fast as it can when using its own resources, but
slows down when it goes "off-board".  It's also a little more expensive, and
works best with operating systems (including BIOS) that permit easy concurrent
I/O and compute...which the IBM PC family does not do.
Fm: Charles Hart 72755,500 17-Dec-86
To: Stephen Satchell 72736,70 (X)
Curious things are happening in the AT Clone marketplace.  I just tested two
motherboards and found the following:
                                        8 Mh 0 WS              10 Mh 0 WS
                                        ---------              ---------
Norton SI                                9.1                     10.3
SSE-V2                                   27(5.1)                 27(5.1)
Crystals were ~16 Mh and ~20 Mh respectively.  Wonder why Norton says 13%
faster when SSE-V2 thinks it's the same board?
P.S. - The 8 Mh was from the Far East while the 10 Mh was from the US. Must
admit the US board "looked" more sturdy and better put together.
Fm: Stephen Satchell 72736,70 17-Dec-86
To: Charles Hart 72755,500
You may have run into a software problem.  I ran into something similar with my
benchmarks when I was doing the Compaq 386 box.  The machine was just too fast
for the benchmarks!  I had to completely re-write the timing part.  I did such
a good job that I can take the programs and run them on anything from a 8 khz
("sounds") 8088 system to a Cray-2 (so long as there is a suitable C compiler
for both).
I suspect that a new version of SI will appear "real soon now"...
@* THE TESTS CONFOUND THEORY
Fm: Gene Saunders 72265,23 21-Dec-86
To: Stephen Satchell 72736,70
          PC Labs Benchmark Series - Release 4.01 - October 1986
BENCH20 - Memory Access Speed Benchmark Test
Version 1.12
Times are in seconds            8088     80286       80286     80286
                                4.77      6/0         8/0      10/1
                             ---------  ---------  ---------  ---------
Conventional read                   -       1.32       0.93       0.99
Conventional write                  -       1.26       0.93       1.05
Extended read                       -          -      16.59          -
Extended write                      -          -      16.59          -
Couldn't run test on 8088 due to RAM limit on demo machine.
Couldn't run extended read/write due to RAM limit on demo machines.
=======================================================================
BENCH21 - Processor Speed Benchmark Test
Version 1.31
Times are in seconds           8088       80286      80286      80286
                               4.77        6/0        8/0       10/1
                             ---------  ---------  ---------  ---------
128K NOP                        10.21       5.55       4.18       3.35
Do nothing                       9.94       4.22       2.97       2.86
Integer add                      9.89       2.47       1.81       1.71
Integer multiply                10.00       1.53       1.10       0.93
String sort and move            10.82       3.30       2.36       2.26
Prime Number Sieve              15.49       4.67       3.35       3.30
=======================================================================
BENCH29 - Floating Point Math Coprocessor Test
Version 1.01
Times are in seconds           8088       80286     80286      80286
                               4.77        6/0       8/0        10/1
                             ---------  ---------  ---------  ---------
Floating point (no 80287)     160.88       44.00      28.07      28.02
Floating point (with 80287)         -          -       3.19          -
Interesting, eh? Re: the BENCH21 test -- it ain't necessaerily so that
an 8 MHz/0 wait will be faster than a 10 MHz/1 wait box. Assamatter of fact,
the 10/1 *slightly*, *only slightly* outperformed the 8/0 machine. For my
test, all CPUs are from the same manufacturer, and all are production models.
The 8/0 and 10/1 boxes have 120 ns DRAM; the 8088 and 80286 are using 150 ns
chips.  All RAM is on the motherboard of each machine.
Fm: Doug Hogarth [PowerSoft] 76703,374 21-Dec-86
To: Gene Saunders 72265,23
That is interesting - we had expected the opposite results - that the 8/0 would
slightly outperform the 10/1.
Fm: Pete Holsberg 70240,334 21-Dec-86
To: Gene Saunders 72265,23
Very interesting.  Do you know how the wait states are implemented?  That is,
one each bus cycle?  One each memory access bus cycle?  Etc.  Can you tell us
what computers you used?
Fm: Gene Saunders 72265,23 23-Dec-86
To: Pete Holsberg 70240,334 (X)
I don't know what the timing is on each bus, although that should be of
importance only when something *other* than pure CPU is concerned, correct?
(i.e. if the test were hard disk related, they would be tied to the controller
and the drive).  Computers used are all of one manufacturer: ITT. The 8088 is
the ITT XTRA.  The 80286/6 MHz-0 wait is the ITT XP. The 80286/8 MHz-0 wait is
the ITT XL. The 80286/10 MHz-1 wait is the ITT 286/ATW.
Fm: Pete Holsberg 70240,334 24-Dec-86
To: Gene Saunders 72265,23
Not exactly.  The CPU is never used alone; it's gotta have the instructions
from memory, right?  So the memory wait states are the most significant.  Now,
a good design would put waits states ONLY where needed, but a cheap design
would add a wait state to every bus cycle.
Fm: Dave Hoagland 76054,171 22-Dec-86
To: Pete Holsberg 70240,334
His experience confirms some tests we conducted Friday.  The single wait state
8mhz IBM AT outperforms the zero wait state 6mhz IBM XT286.  By a reasonable
margin.  Interesting...
Fm: Pete Holsberg 70240,334 22-Dec-86
To: Dave Hoagland 76054,171 (X)
Wow!  That means that wait states are included only on memory accesses.  That's
more expensive than either 1 wait on everything or even 0 waits on every cycle.
And the higher-speed-1-wait-state-on-memory-only will give a significant
improvement on all internal operations, too.
Fm: Dave Hoagland 76054,171 24-Dec-86
To: Gene Saunders 72265,23
I ran the PC Mag BENCHMARK on a new IBM AT (8mhz, 1 wait state) and on an XT286
(6mhz, 0 wait state), and the 8mhz AT came out on top...by a fair margin.  I
don't think your results were in error.  I'm just not sure that we fully
understand the way the wait states are being implemented.  One of my college
professors would have had a fit though...he was a believer that "if the data
doesn't agree with the theory, they must be disposed of". <grin>
Incidentally, my impressions of the relative speeds of the machines after a
month or so of use correlated with the BENCHMARK results...that is, the 8mhz AT
seems to be a faster machine than the XT286...
Fm: John Edward Miller 76011,2122 26-Dec-86
To: STAN DVOSKIN 72477,160
Your comment about 'add-on cards' struck a nerve...if you plan on using the
machine in a networking environment, you may find that 0 wait states on the bus
outruns the network adapter card.  No substitute for a money-back guarantee (or
jumperable wait states, or just a faster network card).
DL 0 !