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- WHAT'S NEW IN VERSION 1.16
- --------------------------
-
- - If revision C or later of the Chips and Technologies 82C302 memory
- controller chip is found, LASTBYTE automatically enables the "Fast
- CAS precharge time" to eliminate the extra wait state when a read
- cycle is immediately followed by a write cycle to the same bank.
-
- NOTE: This capability was not provided in earlier versions
- of the 82C302, and thus most CMOS configuration menus don't
- give you the ability to enable this feature. It corresponds
- to setting bits 5 and 4 of register 20 (hex) in the 82C302c;
- this register does not exist prior to revision C. You can
- determine which you have simply by checking the LASTBYTE.SYS
- information screen. If it indicates "82C302" but not "82C302c",
- then you may want to consider replacing the chip with the newer
- version for a bit more performance.
-
- - Improved the repeatability/reliability of the hardware signature
- computation.
-
- Please let me know if your PC reports "different hardware
- detected - run LICENSE again" and you haven't changed your
- configuration. I'll try to find out what's causing it and
- fix it.
-
- - Reduced the upper memory overhead of LASTBYTE.SYS from 2,704 to
- 1,840 bytes.
-
- - Corrected some bugs in code that supports the following chips:
-
- 82C222 - From the CHIPS/250 PS/2 50/60 chipset
- 82C235 - The SCAT (tm) Single Chip AT VLSI chip
- 82C311 - From the CS8233 PEAK 386/AT CHIPSet (tm)
- 82C322 - From the CHIPS/280 PS/2 70/80 chipset
- 82C202 - From VLSI Technologies' PC/AT chipset
-
- - Improved the handling of PCs with cache controllers, including a new
- command line option "CACHE" to force such recognition.
-
- - Improved the computation of memory bandwidth.
-