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Text File  |  1993-01-25  |  1.1 KB  |  38 lines
  1. Newsgroups: comp.sys.sun.hardware
  2. Path: sparky!uunet!spool.mu.edu!yale.edu!newsserver.jvnc.net!princeton!moo!awolfe
  3. From: awolfe@moo.Princeton.EDU (Andrew Wolfe)
  4. Subject: Re: Performance of Sparc Classic?
  5. Message-ID: <1993Jan25.234012.9459@Princeton.EDU>
  6. Originator: news@nimaster
  7. Keywords: classic sparc performance spec mips mflops benchmarks
  8. Sender: news@Princeton.EDU (USENET News System)
  9. Nntp-Posting-Host: moo.princeton.edu
  10. Organization: Princeton University
  11. References: <phoenix.727660358@well.sf.ca.us> <51917@seismo.CSS.GOV>
  12. Date: Mon, 25 Jan 1993 23:40:12 GMT
  13. Lines: 23
  14.  
  15. In article <51917@seismo.CSS.GOV>, dsc@seismo.CSS.GOV (taste is the enemy of art) writes:
  16. |> 
  17. |> 2        21.8        22.8        28.5    4.2    64    16
  18. |> Classic        26.4        21.0        59.1    4.6    6    64
  19. |> LX        26.4        21.0        59.1    4.6    6    64
  20. |> 10/20        39.8        46.6        77.5    9.5    16/20    65536
  21. |> 
  22. |> * in KBs - cache is unified unless marked as data/instruction.
  23. |> + also has a 1 MB external cache.
  24.  
  25.  
  26.  
  27. I believe that the Classic/LX have 4k+2K caches, not 6K unified.
  28.  
  29. (Based on Hot-Chips Tsunami presentation)
  30.  
  31.  
  32. -- 
  33. --------------------------------------
  34. Andrew Wolfe
  35. Assistant Professor
  36. Department of Electrical Engineering
  37. Princeton University
  38.