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- Path: sparky!uunet!ogicse!hsdndev!newsfeed.rice.edu!rice!abuhr
- From: abuhr@owlnet.rice.edu (Aaron M. Buhr)
- Newsgroups: comp.sys.ibm.pc.games
- Subject: Re: 3D Bench
- Message-ID: <C1Hp17.9GH@rice.edu>
- Date: 27 Jan 93 01:48:43 GMT
- Article-I.D.: rice.C1Hp17.9GH
- References: <1993Jan25.185933.35861@rchland.ibm.com> <C1FvAI.Lv3@rice.edu> <1323@pascal.einstein.eds.com>
- Sender: news@rice.edu (News)
- Organization: Rice University
- Lines: 21
-
- In article <1323@pascal.einstein.eds.com> tobey@einstein.eds.com (Christopher Tobey) writes:
- >< I think these figures given by various simulators need to be taken with
- >< a rather large grain of salt. I have trouble believing that the slowest
- >< member of the Power architecture can emulate a 486 at speed equivalent to
- >< ^^^^^^^^^^^^^^^^^^
-
- >I have trouble believing that you think an IBM RS/6000 uses Power
- >architecture. It uses RISC. The Power architecture is a joint
- >development by IBM, Apple and Motorola. It will be a 64-bit
- >processor when it comes out in 1994.
-
- The RS/6000 _does_ use the Power architecture, which was developed at
- IBM. The IBM/Apple/Motorola joint venture is to produce the Power_PC_. The
- Power_PC_ chip is going to incorporate the features that it takes the
- RS/6000 several chips to handle, throw out some of the less-used features,
- and change the bus interface to resemble (copy?) the Motorola 88100 bus
- interface.
-
-
- Aaron Buhr
- abuhr@owlnet.rice.edu
-