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- From: hyc@hanauma.jpl.nasa.gov (Howard Chu)
- Newsgroups: comp.sys.atari.st
- Subject: Re: Falcon, Falcon who has got a Falcon
- Date: 28 Jan 1993 05:19:32 GMT
- Organization: SAR Systems Development & Processing, JPL
- Lines: 29
- Message-ID: <1k7qd4INN464@elroy.jpl.nasa.gov>
- References: <11809@uqcspe.cs.uq.oz.au> <1993Jan22.162113.13989@bsu-ucs> <1js5r7INNevj@rs2.hrz.th-darmstadt.de>
- NNTP-Posting-Host: hanauma.jpl.nasa.gov
-
- In article <1js5r7INNevj@rs2.hrz.th-darmstadt.de> wallmann@backus.pu.informatik.th-darmstadt.de (Natuerlich!) writes:
- >In article <1993Jan22.162113.13989@bsu-ucs> 01mbmccabe@leo.bsuvc.bsu.edu writes:
- >>> You see, the CPU doesn't spend all it's time accessing memory. Many
- >>> instructions involve no memory access at all. Others access memory,
- >>> but also spend a lot of time processing the instruction. And if an
- >>> instruction or data is already in the on-chip cache, it will be just as
- >>> fast regardless of the bus width.
- >What about if a DMA transfer is going on, is this done over the video
- >(32 bit part) ?
-
- Good question, dunno what a good test would be.
- >
- >>can someone make a list of typical sorts of programs that would be really
- >>"memory-intensive" so as to really suffer from this 16-bit memory bus?
- >>
- >Anything that's video intensive f.e.
-
- Note that in the monochrome video modes, the bustest program (posted here
- last December?) shows no slowdown whatsoever for 16 bit accesses, and less
- than .01% slowdown for 32 bit accesses. (I.e., the 68030 cache delivers
- 100% of the theoretical performance.) I posted my timing results to both
- this group and comp.sys.amiga.advocacy; I am still waiting to see the
- equivalent results for an A1200. If you need the source code again I will
- send it to you; I rewrote it in MIT syntax (for GAS) and still have the
- original Motorola syntax posting.
- --
- -- Howard Chu @ Jet Propulsion Laboratory, Pasadena, CA
-
- There's a rough border between genius and insanity, but I'm a dual citizen.
-