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- Path: sparky!uunet!cs.utexas.edu!natinst.com!natinst.com!not-for-mail
- From: glens@natinst.com (Glen Sescila)
- Newsgroups: comp.sys.atari.st
- Subject: Re: 030 sync cycles (was : A1200 versus Falcon 030 once again)
- Date: 22 Jan 1993 07:25:44 -0600
- Organization: National Instruments, Austin, TX
- Lines: 22
- Message-ID: <1joskoINNqm@falcon.natinst.com>
- References: <H.6a78NGVZTA2@fredrik.atari.no> <1982@enst.enst.fr>
- NNTP-Posting-Host: falcon.natinst.com
- Keywords: STERM
-
- In article <1982@enst.enst.fr> elendir@inf.enst.fr writes:
- >Joern Moe writes
- >] In the falcon they use sync
- >] mode on a 16 bit bus. This gives a 4 clock cycle for each longword
- >] access to the bus. This implies a 25% reduction in performance, not 50%.
- >
- > That is wrong. Synchrone cycles on the 68030 (i.e. those terminated by STERM
- >rather than DSACK) must be 32-bit wide. Refer to the 030 User s Manual. There
- >is no other way than DSACK to end a 16-bit wide exchange.
- >
- >Vincent.
-
- That is wrong. The external hardware (external to the cpu) could do 2 16
- bit cycles and pack them into 1 32 bit. I'm not saying thats what the Falcon
- does but be careful when you use words like 'never' and 'no other way'.
-
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- "Now You're Playing With Power Without The Price!" Glen Sescila |||
- / | \
- My opinions do not necessarily reflect those of my employer and probably are
- exact opposites. InterNet: glens@natinst.com
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