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- Newsgroups: comp.cad.cadence
- Path: sparky!uunet!ukma!darwin.sura.net!sgiblab!munnari.oz.au!titan!pogo!guillaum
- From: guillaum@pogo.trl.OZ.AU (Andrew Guillaume)
- Subject: Verilog-XL reference manual
- Message-ID: <1993Jan28.001406.13597@trl.oz.au>
- Followup-To: comp.cad.cadence
- Sender: root@trl.oz.au (System PRIVILEGED Account)
- Reply-To: a.guillaume@trl.oz.au
- Organization: The Okefenokee Swamp
- Date: Thu, 28 Jan 1993 00:14:06 GMT
- Lines: 27
-
- G'day !
-
- Is my Verilog-XL manual the only one that seems incomplete, or am I missing
- parts of it? The version I have is 1.6 (March 1991), and I'm frustrated at
- not being able to find information about various things.
-
- Take for example the $gr_waves and $gr_regs stuff. Index points to page
- 19-9. Page 19-9 lists these two system tasks as system operations that can
- access protected data, but there's nothing about the the tasks themselves.
- No syntax, no usage, zilch. Another example. Take $bitstoreal and $realtobits.
- Page 20-37. Says these functions convert bits (or real numbers) to real
- numbers (or bits. Says they convert from real to the 64-bit representation
- of that real number. But according to what ? An IEEE standard of some type ?
-
- I'm a novice at verilog, and this reference manual isn't helping me one bit.
- Does anybody have other suggestions as to reference material ?
-
- Also, a behavioural example I'm working on requires the multiplication of
- a number by 2**(-6) (that's 2 to the power -6). I can't find an exponentiation
- function, so does that mean I must create my own ? Are there libraries around ?
-
- Thanks in advance for any info.
-
- Andrew Guillaume
- TRL, Melbourne, Australia
-
- Thought for the day: eschew obfuscation !
-