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- Path: sparky!uunet!noc.near.net!hri.com!spool.mu.edu!howland.reston.ans.net!paladin.american.edu!auvm!!JOHNSON,
- From: DJOHNSON@GEEL.DWT.CSIRO.AU (David Johnson,
- CSIRO Div. Wool Tech.)
- Newsgroups: bit.listserv.i-amiga
- Subject: Re: DSP??
- Message-ID: <930126161123.2020126a@GEEL.DWT.CSIRO.AU>
- Date: 26 Jan 93 05:11:23 GMT
- Sender: Info-Amiga List <I-AMIGA@RUTVM1.BITNET>
- Lines: 30
- Comments: Gated by NETNEWS@AUVM.AMERICAN.EDU
- X-Vmsmail-To: SMTP%"I-AMIGA%RUTVM1.BITNET@pucc.Princeton.EDU"
-
- > I'll bite.
- > What is DSP?
- > Desktop S P?
- >
- > jventola@ecn.mass.edu
- > English Department * Massasoit CC * Brockton, MA 02402
-
- Digital Signal Processor
-
- It's a microprocessor optimised for realtime signal processing applications,
- for example, filtering, companding, speech encryption. I've been using a
- TMS320C25 (from Texas Instruments) in an industrial control application.
- This is a fixed point DSP (floating point units do exist, e.g. TMS320C40).
- The main difference between this DSP and other (conventional) microprocessors
- is its highly pipelined architecture. While it processes one instruction,
- it is simultaneously getting the data for the next instruction, decoding
- the one after that, and fetching the one after that again. Phew! There is
- also a bit of parallelisation, so that each instruction can do multiple
- things: e.g. add data to accumulator, increment an address pointer and
- alter a pointer register all at once. The upshot of all this is that the chip
- completes processing most instructions at the rate of one _every_ clock cycle.
- At 40MHz (the one I'm using), this is one instruction every 100ns. There is,
- however, a catch: conditional branches force the pipeline to be flushed, and
- the instruction set is not as general purpose as you might expect in something
- like a 68000.
-
- hope this clears thing up
-
- dave
- djohnson@geel.dwt.csiro.au
-