NetNews Usenet Archive 1993 #1/NN_1993_1.iso/spool/comp/sys/mips/1165

Internet Message Format | 1993-01-12 | 1.8 KB

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From: [e-mail] (Amer Diwan)
Newsgroups: comp.sys.mips
Subject: Questions about the R3000 cache
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Date: 12 Jan 93 21:52:06 GMT
Article-I.D.: QUICK.ADIWAN.93Jan12165206
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I am collecting memory reference traces from ML programs compiled with SML/NJ
compiler and running them through cache simulators (dinero/tycho).  I am doing
this on DECStations 5000/120 and DECStations 5000/200 running Mach.  For
me to be able to accurately evaluate the effects of memory access patterns on
the running time of the programs, I need to have a detailed understanding of
the write buffer behavior.  I need answers to the following:

1. Latency of a write hit when the write buffer is empty
2. Latency of a write hit when the write buffer is full
3. Latency of a write miss when the write buffer is empty
4. Latency of a write miss when the write buffer is full

The DS5000/200 specs. seem to answer at least 3: 13 cycles (CPU cache fill).
What about the rest?

Are there any trace driven simulators out there that take the write buffer
into consideration?

Other questions: is the R3000 cache write-allocate?  If so, does it do
sub-block replacement or is a whole cache line brought in at once on a write
miss?

Thanks a lot.
    Amer
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Amer Diwan                    School of Computer Science
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[e-mail]                Carnegie Mellon University
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