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- Path: sparky!uunet!munnari.oz.au!uniwa!john
- From: john@gu.uwa.edu.au (John West)
- Newsgroups: comp.sys.m68k
- Subject: Re: state of data bus during write of byte
- Date: 7 Jan 1993 16:02:24 GMT
- Organization: The University of Western Australia
- Lines: 21
- Message-ID: <1ihk6gINNlve@uniwa.uwa.edu.au>
- References: <C0HMG2.322@hermes.hrz.uni-bielefeld.de>
- NNTP-Posting-Host: mackerel.gu.uwa.edu.au
-
- iikoch@techfak.uni-bielefeld.de (Ingolf Koch) writes:
-
- >Hello,
- >can anyone of you out there tell me what happens to the unused wires
- >of the data bus coming out of the 68000 if a byte (8bit) value is
- >written to RAM.
-
- The same data is sent to both halves of the bus. This can get very
- embarrasing when you've wired your DUART to the wrong half of the bus.
- Very odd - you can send data down the line perfectly happily, but for
- some strange reason, nothing will go the other way.
-
- >What about other 680x0 (especially the 68040)?
-
- I think it copies the data onto all parts of the bus, but I can't find
- the relevant bit in the book. Actually, I think it must, or the dynamic
- bus sizing won't work.
-
- John West
- --
- For the humour impaired: Insert a :-) after every third word
-