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- Newsgroups: comp.sys.intel
- Path: sparky!uunet!mcsun!Germany.EU.net!rz.uni-hildesheim.de!ix.de!hm
- From: hm@opus40.ix.de (Harald Milz)
- Subject: Re: 486SL dropped, vendors test Cyrix
- Message-ID: <1993Jan7.174211.27473@opus40.ix.de>
- Sender: hm@opus40.ix.de (Harald Milz)
- Organization: iX-Redaktion
- References: <1993Jan4.155415.2710@crd.ge.com> <C0E0zB.DwG@inews.Intel.COM> <1993Jan6.124308.21857@grebyn.com>
- Date: Thu, 7 Jan 1993 17:42:11 GMT
- Lines: 15
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- |> The Cyrix 486SLC has a 386SX pinout, which means it has a 16 bit data
- |> bus. The 486SX has a 32 bit data bus. Considering the smaller cache
- |> in the Cyrix, I would expect it to be much slower than the 486SX. The
- |> Cyrix 486DLC will be closer, but still slower than a 486SX, mostly
- |> because of the smaller cache, but also because the 486SX bus can be
- |> faster than the 386 bus of the 486DLC chip.
-
- Actually, I think, the 486SLC is an optimized 386 with this small cache.
- The only reason for naming it 486 is marketing.
- --
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