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- Newsgroups: comp.lsi.cad
- Path: sparky!uunet!psinntp!xilinx!philip
- From: philip@xilinx.com (Philip Freidin)
- Subject: Re: Why no tri-state outputs in FPGA cells?
- Message-ID: <1993Jan8.194744.21580@xilinx.com>
- Sender: usenet@xilinx.com
- Organization: Xilinx Inc.
- References: <1992Dec14.221541.25270@dartvax.dartmouth.edu> <1992Dec24.013854.11226@trilobyte.com> <16200@auspex-gw.auspex.com>
- Date: Fri, 8 Jan 1993 19:47:44 GMT
- Lines: 34
-
- In article <16200@auspex-gw.auspex.com> daryl@bovill.auspex.com (Daryl Starr) writes:
- >I have heard from a gate array vendor that internal tristate requires lots
- >of power (I assume from floating inputs being affected by noise) and thus
- >has not been allowed. I would think that FPGA cells would be susceptible
- >to the same problem.
- >
- >Daryl
-
- Some time ago I posted an article detailing how our wonderful chips solve
- this problem. Briefly:
- Internal tristates can draw more than normal power under two
- conditions, Contention and Floating nets.
-
- Contention is fixed by doing your design right, and not letting
- it happen.
-
- Floating nets are an issue if they float for more than a few
- nanoseconds. They can drift to VDD/2 which will cause recievers
- to draw continuous power (a few mA each). The Xilinx chips solve
- this with a circuit called a "weak keeper", that sustains the
- net value after the driver has been three-stated.
-
- Note that other FPGA vendors that have three-state drivers do not have this
- circiut, and so could get into problems if three state nets are left to
- float.
-
- Philip
-
-
- --
- Philip Freidin: Product Planning Manager, Xilinx, INC
- (rest of clever .sig still under construction....
- coming to a terminal near you, Real Soon Now (tm))
-
-