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Internet Message Format  |  1993-01-05  |  774 b 

  1. Xref: sparky comp.lsi.cad:1257 comp.arch:12065
  2. Path: sparky!uunet!auspex-gw!bovill!daryl
  3. From: daryl@bovill.auspex.com (Daryl Starr)
  4. Newsgroups: comp.lsi.cad,comp.arch
  5. Subject: Re: Why no tri-state outputs in FPGA cells?
  6. Message-ID: <16200@auspex-gw.auspex.com>
  7. Date: 4 Jan 93 17:09:02 GMT
  8. References: <1992Dec14.221541.25270@dartvax.dartmouth.edu> <1992Dec24.013854.11226@trilobyte.com>
  9. Sender: news@auspex-gw.auspex.com
  10. Followup-To: comp.lsi.cad
  11. Organization: Auspex Systems
  12. Lines: 6
  13. Nntp-Posting-Host: bovill.auspex.com
  14.  
  15. I have heard from a gate array vendor that internal tristate requires lots
  16. of power (I assume from floating inputs being affected by noise) and thus
  17. has not been allowed. I would think that FPGA cells would be susceptible
  18. to the same problem.
  19.  
  20. Daryl
  21.