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- Xref: sparky comp.lsi.cad:1257 comp.arch:12065
- Path: sparky!uunet!auspex-gw!bovill!daryl
- From: daryl@bovill.auspex.com (Daryl Starr)
- Newsgroups: comp.lsi.cad,comp.arch
- Subject: Re: Why no tri-state outputs in FPGA cells?
- Message-ID: <16200@auspex-gw.auspex.com>
- Date: 4 Jan 93 17:09:02 GMT
- References: <1992Dec14.221541.25270@dartvax.dartmouth.edu> <1992Dec24.013854.11226@trilobyte.com>
- Sender: news@auspex-gw.auspex.com
- Followup-To: comp.lsi.cad
- Organization: Auspex Systems
- Lines: 6
- Nntp-Posting-Host: bovill.auspex.com
-
- I have heard from a gate array vendor that internal tristate requires lots
- of power (I assume from floating inputs being affected by noise) and thus
- has not been allowed. I would think that FPGA cells would be susceptible
- to the same problem.
-
- Daryl
-