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- From: wff@icf.hrb.com (W. Figurelle)
- Newsgroups: comp.lang.vhdl
- Subject: Questions on I/O
- Message-ID: <1993Jan8.093151.19905@icf.hrb.com>
- Date: 8 Jan 93 14:31:50 GMT
- Organization: HRB Systems, Inc.
- Lines: 16
-
- I'm currently writing a test bench for a model and I have a couple
- of questions.
-
- 1) Does VHDL have any hooks provided to take in user input during
- run time? (Ex. prompting for information)
-
- 2) If (1) is possible, is there a way to prompt the user for a
- filename, and then use this in a file object declaration?
- (Ex. FILE myfile:text IS IN input_variable_name)
- I've only seen hardcoded or generic map implementations of this.
-
- The reason for these questions is that I want to write only one test
- bench, and then use this test bench for multiple input stimulus files.
- I know there are ways around this, but I want something efficient.
-
- Thanks in advance
-