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- Newsgroups: comp.lang.vhdl
- Path: sparky!uunet!clsi!kevin
- From: kevin@clsi.COM (Kevin Cameron)
- Subject: Re: data types, vhdl
- Message-ID: <1993Jan4.201803.11646@clsi.COM>
- Originator: kevin@dubhe
- Sender: usenet@clsi.COM
- Reply-To: kevin@clsi.com
- Organization: CAD Language Systems Inc.
- Date: Mon, 4 Jan 93 20:18:03 GMT
- Lines: 37
-
-
- In article <C08p03.Htv@ucunix.san.uc.edu> you write:
- > Hi folks,
- >
- > Is there any options in the vhdl language that lets me declare types
- > equivalent to the "union" in C. The brute force method that I can think of
- > is to declare a record with all the possible choices in the original union
- > as a strictly present field; and have integer tags to access the types:
- >
- > e.g. -- pseudo vhdl code;
- >
- > type union is record
- > -- the tag to determine what field to use;
- > access_type : integer;
- > -- this is where the union starts
- > -- list is declared earlier as an access type to a list;
- > u1 : real;
- > u2 : integer;
- > u3 : list
- > end record;
- >
- > Is there any alternative to this lengthy way of designing a data structure.
- >
- >
- > thanks for any replies and comments.
-
- Use one field of a type large enough to store each member of the union, and use
- type conversion functions depending on the tag value. This is ineffecient in speed
- but more efficient in storage (particularly for signals) - some type conversions
- will be difficult too.
-
- Kev.
- --
- Kevin Cameron CLSI, Suite 100, 5457 Twin Knolls Rd., MD 21045, USA
- kevin@clsi.com Tel: (USA) (410) 992 5700 (- 5709) x224
- uunet!clsi.com!kevin Fax: (410) 992 3536
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