NetNews Usenet Archive 1992 #31/NN_1992_31.iso/spool/comp/sys/ibm/pc/hardware/34094

Internet Message Format | 1992-12-23 | 1.9 KB

Path: sparky!uunet!noc.near.net!nic.umass.edu!dime!freya.cs.umass.edu!doyle
From: [e-mail]
Newsgroups: comp.sys.ibm.pc.hardware
Subject: Talk about hardware issues for i486 multiprocessor
Message-ID: <[e-mail]>
Date: 23 Dec 92 20:45:56 GMT
Sender: [e-mail]
Organization: University of Massachusetts, Amherst
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Originator: [e-mail]


    I was wondering if anyone would like to discuss issues that
pertain to multiprocessing on PC architecture machines. It has been some
time since I've played in the hdware sandbox of the ix86 world - much
has changed. In particular, I'd like address the two areas that are crucial
to the possibility of SMP on standard, low-cost, high-volume hardware:
bus technologies and cache controller chips.

    As far as I know, EISA provides not only high-bandwith but also
multiple bus master arbitration facilities. What about the new LocalBus (VL)
technology - does it support standard signalling to allow for multiple
bus masters to contend for the common systems bus?

    What about arbitration methodology? In both the case of EISA and
VL bus technology, does bus arbitration logic allow for the guaranteed
mastership during execution of atomic memory operations (CAS,TAS, etc.) ?
These are critical to maintaining synchronization and semaphore locking
in the OS kernel.

    Finally, we have to look at issues of cache coherency. Are there
any chipsets on the market which are capable of doing bus-snooping ??

    I've done alot of work with Mach 3.0 on an i486 box. In an upcoming
job, I will be porting Mach 3.0 to a symmetric multiprocessor SGI PowerSeries
box (eight MIPS R3000's). In the future, there maybe some interest in using
my knowledge to due a similar implementation on cheap, commercial i486
hardware provided that the existing hardware base can accomodate.

..... Jim Doyle   ([e-mail] , [e-mail] )