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- From: mlelstv@speckled.mpifr-bonn.mpg.de (Michael van Elst)
- Subject: Re: Chunky Pixels vs. Bitplanes (was: Chunky Chip Set...)
- Message-ID: <1992Dec31.173317.10781@mpifr-bonn.mpg.de>
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- Organization: Max-Planck-Institut f"ur Radioastronomie
- References: <Karsten_Weiss.0n2o@ibase.stgt.sub.org> <1hbngoINNglt@uwm.edu> <1992Dec30.115759.22097@mpifr-bonn.mpg.de> <doiron.0ka3@starpt.UUCP> <1992Dec31.011428.2926@mpifr-bonn.mpg.de> <1htk0tINN53e@gap.caltech.edu>
- Date: Thu, 31 Dec 1992 17:33:17 GMT
- Lines: 22
-
- In <1htk0tINN53e@gap.caltech.edu> andrey@cco.caltech.edu (Andre T. Yew) writes:
- > Even if you could do custom designs, you generally
- >cannot have free shifting. A standard shift-register
- >design in CMOS usually runs off a two-phase clock, so
- >at best you need two clock ticks between shifts, and shifts
- >need 2 clocks to complete.
-
- Maybe this was a bit misunderstanding. The shifting of course takes
- some time, but because of pipelining in your blitter (and the fact
- that it is still faster than a memory cycle) makes it a no-cost operation.
-
- You may say that you have to fill/flush your pipeline. But that's usually
- hidden by any setup operation. A FIFO for blitter commands might again
- make that visible but it is still only a small fraction of the whole
- blit operation.
-
- Regards,
- --
- Michael van Elst
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