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- Path: sparky!uunet!zaphod.mps.ohio-state.edu!swrinde!elroy.jpl.nasa.gov!news.claremont.edu!nntp-server.caltech.edu!andrey
- From: andrey@cco.caltech.edu (Andre T. Yew)
- Newsgroups: comp.sys.amiga.programmer
- Subject: Re: Chunky Pixels vs. Bitplanes (was: Chunky Chip Set...)
- Date: 31 Dec 1992 01:56:45 GMT
- Organization: California Institute of Technology, Pasadena
- Lines: 20
- Message-ID: <1htk0tINN53e@gap.caltech.edu>
- References: <Karsten_Weiss.0n2o@ibase.stgt.sub.org> <1hbngoINNglt@uwm.edu> <1992Dec30.115759.22097@mpifr-bonn.mpg.de> <doiron.0ka3@starpt.UUCP> <1992Dec31.011428.2926@mpifr-bonn.mpg.de>
- NNTP-Posting-Host: punisher.caltech.edu
-
- mlelstv@specklec.mpifr-bonn.mpg.de (Michael van Elst) writes:
-
- >In <doiron.0ka3@starpt.UUCP> doiron@starpt.UUCP (Glenn Doiron) writes:
- >>Oh, obviously. If you can make this magical piece of hardware, I'm sure
- >>Commodore has a job position open for you. Or any other number of chip
- >>designers.
-
- >I could probably make that from discrete parts of fpgas but I have no
- >experience in doing asics or even full custom designs.
-
- Even if you could do custom designs, you generally
- cannot have free shifting. A standard shift-register
- design in CMOS usually runs off a two-phase clock, so
- at best you need two clock ticks between shifts, and shifts
- need 2 clocks to complete.
-
- --Andre
-
- --
- Andre Yew andrey@cco.caltech.edu (131.215.139.2)
-