home *** CD-ROM | disk | FTP | other *** search
- Path: sparky!uunet!sybus.sybus.com!myrddin!tscs!tbag!jayson
- From: jayson@tbag.tscs.com (Jayson Phillips)
- Newsgroups: comp.sys.amiga.advocacy
- Subject: re: 300 MIPS Amiga
- Message-ID: <jayson.04q0@tbag.tscs.com>
- Date: 22 Dec 92 03:32:18 EST
- Organization: Tampa Bay Amiga Group
- Lines: 83
-
-
- 11 Dec 92 06:53:44 GMT dtiberio@engws10.ic.sunysb.edu (David Tiberio) writes:
-
- >In article <jayson.04ha@tbag.tscs.com> jayson@tbag.tscs.com (Jayson Phillips)
- >writes:
- >
- >>I really like the 68K CPU series but, so what. There are already 100MIPS+
- >>processors now (like the Motorola 88110). There will probably be 200MIPS
- >>processors by 1995 (maybe even 1994) so this puts the 200MIPS 68K about 5
- >>years behind the rest of the world. The 68K line has been a good solid
- >>performer but as time goes by new processors incorporate the advantage of
- >>new design and fabrication technoloy.
- >
- > CISC = COMPLICATED Instruction Set
-
- Actually: CISC = Complex Instruction Set Computer (no big deal)
-
- > RISC = REDUCED Instruction Set
- >
- > Let's see who outperforms who: The 100 MIP Argo RISC vs
- > the 33 MIP Blik CISC
-
- [interesting seudo code for the two "CPU's" deleted]
-
- >
- > Okay, now of the two above routines, the RISC is running 3 times
- >faster but has to execute 5 times as many instructions, causing it to be
- >SLOWER than the CISC chip.
- >
- > Is that understood?
-
- Your point is well taken but you're assuming your own personal definition
- of "MIPS" where as I am assuming a standard (used by Motorola) of *VAX*
- MIPS that is based on Dhrystone 2.1 which does not literally refer to an
- instruction count based on any particular architecture.
-
- From Motorola designers:
-
- 68040 25MHz - 20+ VAX MIPS
- 88110 50MHz - 100+ VAX MIPS
-
- SPEC ratings may be more accurate or applicable:
-
- Transistors Integer FloatPoint Combined
- ----------- | ------- ---------- --------
- 68040/25MHz 1.2 million | 12.9 11.0 11.8
- 68060/50Mhz 2.0 million | ---- ---- 46.0 (predicted)
- 88110/50MHz 1.3 million | 51.0 73.9 63.7
-
-
- Quote from IEEE Micro 4/90 page 61:
-
- "As an example, the double-precision floating-point matrix multiply routine
- often used in graphics viewpoint transformations is illistrated in Figure
- 26. On this code the 88110 can issue two instructions on nearly every
- clock cycle and can sustain 97.5 MIPS and 68 double-precision Mflops (at
- 50MHz), even if the point vectors are not in the cache and the processor is
- operating into DRAM."
-
- My main point is not to debate CISC/RISC or MIPS/FLOPS but that the bottom
- line in compters is the price/performance ratio. *IF* you are considering
- changing to another CPU line (CBM VP said it first) and *IF* the 88110 is
- faster *AND* costs less to manufacture than the 68060, then it makes good
- sence to check it out.
-
- References:
-
- 68040 - Computer Design, Feb 1 1990
- Personal Computing World, April 1990
- (SPEC from HP, posted on the NET)
-
- 68060 - Posted on the NET and on Genie (well, they haven't made it yet)
-
- 88110 - IEEE Micro, April 1992 (a VERY good article)
-
- -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-
- Jay Phillips * Tampa Florida
- Amiga 3000 25Mhz/105HD/10MB
- USENET: tbag!jayson@tscs.com
- -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-
-
- --- Via UCI v1.02 (C-Net Amiga)
-
-