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- Newsgroups: comp.lang.verilog
- Path: sparky!uunet!timbuk.cray.com!walter.cray.com!jake!jwest
- From: jwest@jake (Jeff West)
- Subject: Re: New question - lint like verilog checker
- Message-ID: <1992Dec22.095322.29295@walter.cray.com>
- Lines: 27
- Nntp-Posting-Host: jake.cray.com
- X-Newsreader: Tin 1.1 PL3
- References: <13702@optilink.COM>
- Date: 22 Dec 92 09:53:22 CST
-
- manley@optilink.COM (Terry Manley) writes:
- : In using the verilog language I've noticed the language
- : will allow you to do many things you don't necessarily
- : want to do. Like the C language it is very flexible,
- : unfortunately unlike C there isn't a program verifier
- : like lint. I can think of many things I'd like to be
- : checked, things that if checked would eliminate some
- : of the debugging phase. (My recent post on execution
- : of always blocks is one example, another is missing
- : event triggers for always blocks, or declared but
- : unreferenced reg or wire variables, or ....)
- :
- : Anybody heard of a tool like this?
- :
- : dave
- : manley@optilink.com
-
- There is a tool called Verilint from the Veritools company. I have
- no experience with it though.
-
- Jeff
-
- ---------------------------------------------------------------------
- It's not denial. I'm just very selective about the reality I accept.
-
- - Calvin & Hobbs
-
-