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- Xref: sparky comp.arch:11985 comp.sys.intel:2846
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- From: jesup@cbmvax.commodore.com (Randell Jesup)
- Newsgroups: comp.arch,comp.sys.intel
- Subject: Re: Superscalar vs. multiple CPUs ?
- Message-ID: <38194@cbmvax.commodore.com>
- Date: 29 Dec 92 20:02:47 GMT
- References: <PCG.92Dec11162630@aberdb.aber.ac.uk> <1992Dec21.134531.3253@athena.mit.edu> <PCG.92Dec23144916@decb.aber.ac.uk> <Bzpzwq.18q@news.udel.edu> <PCG.92Dec27201257@decb.aber.ac.uk>
- Reply-To: jesup@cbmvax.commodore.com (Randell Jesup)
- Organization: Commodore, West Chester, PA
- Lines: 38
-
- pcg@aber.ac.uk (Piercarlo Grandi) writes:
- >This is another reason for which I think hyperscalar is premature:
- >a vector instruction has the very nice property that it implies a very
- >definite memory access pattern, as compared with a loop that does the
- >same thing. And many important applications have FIFO data reference
- >patterns, for which predictive memory accesses are essential, and
- >adaptive ones, like those implied by a cache, are fatal:
-
- This is one reason I've been advocating smarter caches, particularily
- the ability to do predictive pre-fetching. There are a couple of ways to
- set this up:
-
- 1. Instruction sets address, bound, and perhaps amount to fetch. Access
- to address causes the next item to be fetched (or it could be more
- aggressive than that, depending on memory latency).
-
- 2. Load instruction encodes prefetch-enable and bounding size in the
- instruction. The problem here is finding enough bits in the
- instruction.
-
- 3. Instruction sets register, bound and perhaps size, and any load
- relative to that register causes a prefetch (the RPM40 data cache
- design included this - never built though). Only works if the
- register number is available to the cache controller.
-
- 4. Prefetch instruction is executed earlier in the instruction stream
- to fetch a location. This is probably the least-useful way to do
- this, certainly it's highest-overhead in cycles (and might require
- more instructions to set up).
-
- --
- -
- GNU Emacs is a LISP operating system disguised as a word processor.
- - Doug Mohney, in comp.arch
-
- Randell Jesup, Jack-of-quite-a-few-trades, Commodore Engineering.
- jesup@cbmvax.commodore.com BIX: rjesup
- Disclaimer: Nothing I say is anything other than my personal opinion.
-