NetNews Usenet Archive 1992 #31/NN_1992_31.iso/spool/comp/arch/11915

Text File | 1992-12-23 | 4.1 KB | 78 lines

Newsgroups: comp.arch
Path: sparky!uunet!paladin.american.edu!gatech!rpi!usc!enterpoop.mit.edu!linus!philabs!acheron!scifi!watson!yktnews!admin!signa!cecchi
From: [e-mail] (Del Cecchi)
Subject: Re: IBM AS/400 is the world's slowest computer
Message-ID: <[e-mail]>
Sender: [e-mail] (Del Cecchi)
Date: Tue, 22 Dec 1992 20:43:13 GMT
Disclaimer: This posting represents the poster's views, not necessarily those of IBM
References: <[e-mail]> <[e-mail]>
Nntp-Posting-Host: signa.rchland.ibm.com
Organization: IBM Rochester
Lines: 64

In article <[e-mail]>, [e-mail] (Zalman Stern) writes:
|> In article <[e-mail]> [e-mail] (Guy Harris) writes:
|> > >3) The AS400 is a capability based tagged architecture.  It offers
|> security
|> > >    like nothing else on the market.  That's not to say that it's
|> perfect,
|> > >    but while all us RISCy folks have been off worrying about MIPS, IBM
|> has
|> > >    noticed that tools providing incredibly tight control over access to
|> > >    information are crucial in many markets.  Try writing an AS400 virus!
|> >
|> > Just out of curiosity, how much of the capability stuff is implemented
|> > in what I, at least, would consider the *real* instruction set - i.e.,
|> > the so-called "vertical microcode" instruction set - and how much is
|> > implemented in the "high-level" instruction set?
|> >
|> > I.e., precisely how CISCy is the "vertical microcode" instruction set? I
|> > don't particularly care how CISCy the "high-level" instruction set is -
|> > Smalltalk bytecodes are probably somewhat "high-level", as may be the
|> > internal bytecodes used by various language interpreters, but both can
|> > be handled, these days, by non-"high level CISC" processors (both RISC
|> > and CISC).
|>
|> My understanding is the further down you go in instruction sets on the
|> AS/400, the more differences there are between different implementations.
|> That is, the "vertical microcode" instruction set is implementation
|> dependent. Of course my main complaint with incredibly "high level" machines
|> like this is that I've never really been able to understand how they work.
|> My disgust level is exceeded about the point someone says "well though,
|> that's not the instruction set the hardware implements. We have another
|> layer here that..." for the second or third time.

BZZZT. Thanks for playing, better luck next time.  The vertical licensed internal
code (VLIC), which some people used to call vertical microcode, instruction set
 COULD BE implementation dependent, but
is not across the current model line.  There is a Lot of VLIC and it would be
quite a bit of un-necessary work to maintain a bunch of different versions for
different low level instruction sets. But it would be fun to get to design all
those different processors.   So far as I know, the instruction set for
all AS/400's is the same.  But of course we could change it some day AND YOU
WOULDN'T EVEN KNOW. Sort of one of those tree in the forest things... :-).

It's really only one more layer than a "conventional" architecture.  MI is the
high level which protects you from all the nasty details.

|>
|> There was an article in one of "the rags" claiming that IBM is going to do a
|> 64 bit RISC based version of the AS/400. Details on what that means would be
|> very interesting. In particular, is it based on PowerPC or is IBM going to
|> have two 64 bit RISC architectures floating around. Or is it one of these
|> "RISC implementations" rather than a "RISC architecture."
|> --
|> Zalman Stern           [e-mail]            [phone]
|> Adobe Systems, 1585 Charleston Rd., POB 7900, Mountain View, CA 94039-7900
|>   "Yeah. Ask 'em if they'll upgrade my shifters too." Bill Watterson

"IBM doesn't comment on un-announced machines" Any information about such a
machine if anyone is in fact working on such a machine would be confidential and
would not be disclosed,
--

Del Cecchi
[e-mail]
My opinions, not IBM's.