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- From: lindsay+@cs.cmu.edu (Donald Lindsay)
- Newsgroups: comp.arch
- Subject: Re: COMPAQ PROPOSED SCALABLE I/O ARCHITECTURE
- Message-ID: <BzoL0q.3zr.2@cs.cmu.edu>
- Date: 22 Dec 92 21:58:00 GMT
- Article-I.D.: cs.BzoL0q.3zr.2
- References: <1992Dec17.190553.17417@twisto.eng.hou.compaq.com> <1992Dec18.100700.62150@cc.usu.edu> <AJC.92Dec19132456@thendara.pa.dec.com>
- Sender: news@cs.cmu.edu (Usenet News System)
- Organization: School of Computer Science, Carnegie Mellon
- Lines: 15
- Nntp-Posting-Host: gandalf.cs.cmu.edu
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-
- ajc@pa.dec.com (AJ Casamento) writes:
- > I guess I not as upset by the concept of using an ASIC. Of course, I'm not
- >talking about respinning a full custom ASIC for each new design either.
-
- I would expect that the ASICs could become cheap, and would have a lot
- in common internally.
-
- However, ASICs have a lead time. If Compaq is serious about spreading
- this as a standard, then they should make available a
- common-denominator design based on common parts, or on FPGAs.
- Something that lets people get their feet wet, at the very least.
-
- --
- Don D.C.Lindsay Carnegie Mellon Computer Science
-