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- Path: sparky!uunet!olivea!xenitec!zswamp!geoff
- From: geoff@zswamp.UUCP (Geoffrey Welsh)
- Newsgroups: biz.sco.general
- Subject: Re: Performance issues revisited
- Message-ID: <Duw8VB10w165w@zswamp.UUCP>
- Date: 23 Dec 92 04:26:12 GMT
- References: <sheldon.725038896@pv141b.vincent.iastate.edu>
- Organization: Izot's Swamp
- Lines: 27
-
- sheldon@iastate.edu (Steve Sheldon) writes:
-
- > time dd if=/dev/rhd0a of=/dev/null bs=131072 count=128
-
- I know that the DMA controllers on PC-compatibles can't do a transfer of
- more than 64K in a go. In theory, the Adaptec (models 154x, 164x, 174x) need
- not be limited by this, thanks to bus master DMA. Does anyone know the size
- limit for a single DMA burst from these devices?
-
- > I'm curious if perhaps the configuration you have just doesn't like the
- > smaller block size. I suppose it might be possible...
-
- In my own experiments while constructing a count-oriented (for maximum
- performance) yet time-regulated disk benchmark, I found that throughput
- increases logarithmically with block size. (note: not exponentially; I mean
- approaching the maximum, with each increment in block size having less effect
- than the last.) I ended up using 60K blocks, because they gave pretty much
- the same figures as 63K blocks. Some systems gave very low figures when 64K
- block sizes are used, but others did not; I do not understand that
- observation.
-
- Geoffrey Welsh, 7 Strath Humber Court, Islington, Ontario, M9A 4C8 Canada
- geoff@zswamp.uucp, [xenitec.on.ca|m2xenix.psg.com]!zswamp!geoff (416)258-8467
- Now I've lost everything, I give to you my soul
- And the meaning of all that I believed before escapes me
- In this world of none, no thing, and no one
- - Genesis, _Afterglow_
-