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- Newsgroups: sci.electronics
- Path: sparky!uunet!utcsri!utzoo!henry
- From: henry@zoo.toronto.edu (Henry Spencer)
- Subject: Re: Static Column vs. Nibble Mode DRAM?
- Message-ID: <BzD6xH.C74@zoo.toronto.edu>
- Date: Wed, 16 Dec 1992 18:20:04 GMT
- References: <60570032@hpcuhe.cup.hp.com>
- Organization: U of Toronto Zoology
- Lines: 40
-
- In article <60570032@hpcuhe.cup.hp.com> ken@hpcuhe.cup.hp.com (Kenneth M. Sumrall) writes:
- >What is the difference between "Static Column DRAM", "Nibble Mode DRAM", and
- >"Fast Page Mode" DRAM?
-
- Internally, a DRAM is a matrix -- usually square -- of cells, and a read
- operation internally reads out an entire row. Folks noticed that it was
- kind of wasteful to read an entire row out and then supply only one bit
- to the outside world. Of course, if you're reading bits at random, there
- isn't much that can be done about it. But if you're reading them in
- sequence, getting the next bit out of an already-read row is a lot
- quicker than reading a new row. Several ways of exploiting this were
- invented.
-
- In a static-column DRAM, once the row read has been done, you're looking
- at something that behaves much like a static RAM: change the address
- lines, and after a specified access time, that bit shows on the output.
-
- In a page-mode DRAM, you have to clock the new column address in with
- one of the control signals to make things happen. Fast page mode is
- just page mode implemented well; early page-mode implementations often
- were rather slow.
-
- In a nibble-mode DRAM, you feed the first column address in by the usual
- method, and then after that, just wiggle one control line and it increments
- automatically. Usually there's only a two-bit counter, so you can get a
- maximum of four bits out this way, hence "nibble mode".
-
- >Also, what is "Write Per Bit", and why do I want it?
-
- DRAMs whose outside-world interface is wider than one bit have only one
- set of control signals for all N (usually N=4) bits. For many purposes,
- this is fine because you read/write all N bits at once. There are a
- few applications that really want finer control. Consider a 32-bit-wide
- memory implemented with 4-bit-wide DRAMs. Okay, that's 8 chips. Now add
- one parity bit per byte. That's 4 bits, one more chip... except that if
- the system does byte writes into the memory, you need to be able to change
- one of those parity bits without changing the others.
- --
- "God willing... we shall return." | Henry Spencer @ U of Toronto Zoology
- -Gene Cernan, the Moon, Dec 1972 | henry@zoo.toronto.edu utzoo!henry
-