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Text File  |  1992-12-14  |  872 b   |  24 lines
  1. Newsgroups: sci.electronics
  2. Path: sparky!uunet!elroy.jpl.nasa.gov!ames!saimiri.primate.wisc.edu!caen!uvaarpa!murdoch!murdoch.acc.virginia.edu!heyes
  3. From: heyes@dadev.cebaf.gov (Graham Heyes)
  4. Subject: DRAM refresh circuit needed...
  5. Message-ID: <HEYES.92Dec14143216@dadev.cebaf.gov>
  6. Sender: usenet@murdoch.acc.Virginia.EDU
  7. Organization: Continuous Electron Beam Accelerator Facility
  8. Distribution: sci.electronics
  9. Date: Mon, 14 Dec 1992 19:32:16 GMT
  10. Lines: 12
  11.  
  12. Does anyone have an example of how to build a DRAM refresh
  13. circuit using discrete TTL logic with perhaps the odd PAL
  14. thrown in. I have been looking in handbooks from various
  15. memory suppliers and their examples all use DRAM controller
  16. chips. I am trying to keep costs down and want to use parts
  17. I have on hand.
  18.  
  19.     If you ahve anything at all that you can paper mail
  20. or FAX send me an E-mail.
  21.  
  22.     thanks
  23.         Graham Heyes
  24.