NetNews Usenet Archive 1992 #30/NN_1992_30.iso/spool/comp/sys/sun/hardware/6195

Internet Message Format | 1992-12-11 | 1.6 KB

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From: [e-mail] (Gary Hladik)
Newsgroups: comp.sys.sun.hardware,comp.sys.sun.misc
Subject: Need info on IPX, 1+ cache
Message-ID: <[e-mail]>
Date: 12 Dec 92 00:09:53 GMT
Sender: [e-mail]
Reply-To: [e-mail] (Gary Hladik)
Organization: Amdahl Corporation, Sunnyvale CA
Lines: 25

I need some technical information on the SPARC 1+ and IPX workstations.
We're trying to improve a compiled-code logic simulator, and we want to
know if we can make better use of the IPX cache.  BTW, we're also looking
at other options such as event-driven code, so please limit responses to
the following areas:

(1) What are the differences between the 1+ and IPX?  Our benchmarks show
slight improvement on the 1+ when memory access is sequential (instead of
random), and a big improvement on the IPX.  This indicates to me that the
IPX cache (64K?) is much bigger than the 1+.

(2) Is the IPX cache split into partitions for instructions and data,
or is it unified?  One of our simulators has ~450K of instructions vs.
only 12K for data, yet seems to access the data much faster on the IPX
than on the 1+.

(3) Does anyone know the algorithm for evicting lines from the IPX (data?)
cache?  Is it least-recently-used only, least-recently-modified, or what?

(4) Is it possible to get an IPX with expanded cache, or is its cache size
fixed?

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Gary Hladik, Amdahl Corporation, Sunnyvale, Ca. USA
[e-mail]