NetNews Usenet Archive 1992 #30/NN_1992_30.iso/spool/comp/sys/m6809/544

Text File | 1992-12-13 | 2.5 KB | 58 lines

Newsgroups: comp.sys.m6809
Path: sparky!uunet!cs.utexas.edu!milano!cactus.org!ritter
From: [e-mail] (Terry Ritter)
Subject: Re: Is MC6809 microcoded ?
Message-ID: <[e-mail]>
Summary: No, but . . . .
Organization: Capital Area Central Texas UNIX Society, Austin, Tx
References: <[e-mail]> <[e-mail]>
Date: Sun, 13 Dec 1992 06:36:48 GMT
Lines: 46


 While I do not normally monitor this group, a friend asked me to
 look in, because, a decade-and-a-half ago, I was involved in the
 design of the 6809.

 As noted in another post, the 6809 was not microcoded.  But the
 structure was not a horribly-complex sort of centralized-state-
 machine either.

 Essentially, each group of instructions started a "timing chain"
 or sequencer which was really just a simple shift-register.  As
 a bit propagated down a chain, fully-decoded timing was provided
 for one group of instructions.  For us breadboard people, this
 was an advantage because we could work on one well-separated
 instruction group at a time.

 A timing-chain structure provides a close relationship between
 a group of instructions and the equations for that group, which
 to some extent provides a reduction of complexity.  Equation
 minimization becomes somewhat more obvious and direct.  This sort
 of structure is probably easier to understand than a centralized
 state machine.  It need not be slower.

 However, the 6809 did in fact use a huge amount of random logic
 in addition to the simple timing-chains and probably was not very
 efficient in its use of silicon.  We certainly did not have any
 research which addressed the issue at the time; this was just
 the way microprocessors were designed.  From the perspective of
 hindsight, however, I think the single-level random-logic
 structure was overtaxed, and could have been greatly minimized
 with additional decoding levels.   Another cost of a timing-chain
 design is the need to test each chain, but that is probably
 implicit in the need to test every instruction anyway.

 The timing-chain design was not a new innovation for the 6809;
 rather, it was the way that the original 6800 (in Phoenix), the
 depletion load re-do 6800 (in Austin), and other processors were
 done (in Austin).  The 6809 was intended to be expanded from the
 6800 core (similar registers, ALU, etc.).  The 68000 was done
 differently because it was done by a completely separate (new)
 team assembled from the outside and they had different design
 experience.

 ---
 Terry Ritter   [e-mail]