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- From: russotto@eng.umd.edu (Matthew T. Russotto)
- Subject: Re: RISC defined! Was Re: 486SLC chip.... what is it?
- Message-ID: <1992Dec13.150243.26083@eng.umd.edu>
- Date: Sun, 13 Dec 92 15:02:43 GMT
- Organization: Project GLUE, University of Maryland, College Park
- References: <8f8d5m200WAL42H2tB@andrew.cmu.edu> <1992Dec9.230819.7876@mksol.dseg.ti.com> <1992Dec11.155653.8469@ptdcs2.intel.com>
- Lines: 34
-
- In article <1992Dec11.155653.8469@ptdcs2.intel.com> greason@ptdcs2.intel.com (Jeff Greason ~) writes:
- >
- >Aha! Somebody finally admitted it. I've long suspected that the RISC advocate
- >definition of RISC is primarily negative. Originally, RISC chips had simple
- >instruction sets, where "simple" was supposed to make it possible to use
- >advanced implementation techniques such as pipelining and caching because
- >of the reduced transistor budget. When CISC chips used these, they claimed
- >that reduced implementation time was the advantage. Now, it comes down to
- >just what you stated:
- > "RISC (adj.): 1) A chip which does not accept the X86 instruction set.
- > 2) A chip which is not manufactured by Intel."
- >
-
- Not so! Chips which implement the 680X0 instruction set aren't RISC
- either.
-
- >This means that no matter what new tricks you'd like to try, RULE 1 has got
- >to be at least a modest improvement in the execution speed of a significant
- >fraction of existing code! You can speed up new code all you want -- unless
- >you gain an incredible amount (and the market has shown that 1.5X the speed
- >is not "significant" here), the guy who DOES speed up existing code will
- >clean your clock for you.
-
- Then how did Sun move from the Sun 3 to the Sparc? The Sparc doesn't
- run 680X0 stuff at all.
-
-
- Hmm... Does the 80386 run 4004 or 8008 code?
-
- --
- Matthew T. Russotto russotto@eng.umd.edu russotto@wam.umd.edu
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