NetNews Usenet Archive 1992 #30/NN_1992_30.iso/spool/comp/sys/amiga/programm/17584

Internet Message Format | 1992-12-21 | 3.4 KB

Xref: sparky comp.sys.amiga.programmer:17584 comp.sys.amiga.hardware:21836
Path: sparky!uunet!cbmvax!daveh
From: [e-mail] (Dave Haynie)
Newsgroups: comp.sys.amiga.programmer,comp.sys.amiga.hardware
Subject: Re: CISC and RISC
Message-ID: <[e-mail]>
Date: 17 Dec 92 20:44:43 GMT
References: <[e-mail]> <[e-mail]> <[e-mail]> <[e-mail]> <[e-mail]>
Reply-To: [e-mail] (Dave Haynie)
Distribution: world
Organization: Commodore, West Chester, PA
Lines: 49

In article <[e-mail]> [e-mail] (Trent Bills) writes:
>|> Another Advantage of RISC is the abundance of Register memory.

>Since most microprocessor computers have either on chip or external caches,
>register access really isn't much if any faster than memory access.

Sure it is.  It wasn't until recently that on-chip caches hit as fast as
register accesses -- this is true for the 68040 and some RISCs, but hits to
the on-chip caches on 68030 and 80486 take twice as long as register access.
External access, even to cache, will take longer.  Even if there's a very fast
external bus interface, you're still having to occupy the bus interface with a
data cycle if you can't use a register.  When you can use a register, the
external bus interface may be free for I or other D fetch.

But it's actually even worse than that.  Registers are often multiported,
sometimes four-way or more.  Multiple execution units can have simultaneous
read access to a register, effectively cutting it's access time by the
degree of multiporting.  The next generation of on-chip caches are moving
toward interleaving or 2-way porting, but they're still much less efficient
than registers by several times.

>It is important to note that RISC processors that have > 32 registers do
>not have the use of all of these registers simultaneously.  The processor
>only has access to a few (24-32) at a time.  A compiler can then place
>parameters for function calls in the last few registers.  When the
>function call is executed, the CPW (current window pointer) is changed
>so that the registers that were previously the last few are now the first
>few.  This parameter passing technique avoids using the stack (slow memory)
>and thereby drastically reduces the cost (time) of a function call.

This is the approach taken by the SPARC processors.  You can have a function
call advantage, but it can mean that context switches are really expensive.
An interesting alternative approach is used by the AT&T CRISP architecture.
Rather than avoid using the stack, they count on using the stack and put in
what's essentially a stack cache.  Operations run stack-relative, but cached
stack entries behave like registers (since stack cache hits take place in
their own cache, not the D cache, there are no inherent conflicts with other
data fetches that may go on, just like traditional register access).  The
advantage of this is that, like any other cache, only the dirty values need
to be written out on a context switch (or none if you're running with a
write-through cache).


--
Dave Haynie / Commodore Technology, High-End Amiga Systems Design (cool stuff)
 "The Crew That Never Rests"  {uunet|pyramid|rutgers}!cbmvax!daveh   BIX: hazy
        SCIENCE:    "I'll believe it when I see it"
        RELIGION:    "I'll see it when I believe it"