NetNews Usenet Archive 1992 #30/NN_1992_30.iso/spool/comp/sys/amiga/programm/17537

Internet Message Format | 1992-12-21 | 1.6 KB

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From: [e-mail] (Rob McCool)
Subject: Re: CISC and RISC
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Date: Fri, 18 Dec 1992 17:22:26 GMT
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Richard Jones ([e-mail]) wrote:
:   Yes, CISC _is_ easier to program in most cases because the instructions are
: generalized. As for memory writes.. if your chip is doing this then I suggest
: you change manufacturers..

This is hardware interlocking, and there are different approaches used to
  the problem. The problem is memory latency; we all know memory is slow
  and it takes 2 cycles to execute a load. The problem is when someone does
  a load, and then in the next instruction does something to the just-loaded
  data.

The SPARC has interlocking which will insert no-ops into the pipeline if
  there is an instruction which attempts to reference data that is not there
  yet. The MIPS decided to leave out hardware interlocking, and depend on the
  software to do proper instruction scheduling to gain speed, and so if
  you reference data that has not been loaded yet you will get garbage.

--
Rob McCool, NCSA STG System Administrator
[e-mail] [e-mail] [e-mail]
It was working ten minutes ago, I swear...