NetNews Usenet Archive 1992 #30/NN_1992_30.iso/spool/comp/sys/amiga/programm/17508

Internet Message Format | 1992-12-20 | 5.9 KB

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From: [e-mail] (Richard Jones)
Subject: Re: CISC and RISC
Message-ID: <[e-mail]>
Sender: [e-mail] (Usenet system)
Organization: Monash University, Melb., Australia.
References: <[e-mail]> <[e-mail]> <[e-mail]> <[e-mail]>
Date: Fri, 18 Dec 1992 05:00:21 GMT
Lines: 91

[e-mail] (Edsel Adap) writes:
>In article <[e-mail]> [e-mail] (Eric Dewald) writes:
>>Why should computer makers go from CISC to RISC?
>RISC - Reduced Instruction Set Computer
>CISC - Complex Instruction Set Computer
>The reason for many companies going RISC is because of its great speed
>advantages over CISC.  This is accomplished in many ways.  In CISC, (ie a
>Motorolla 68000) the instruction set is what is called a macro instruction.
>These macro instruction are a collection of micro instructions that do what
>the macro instructions is supposed to do.  In RISC instead of a macro
>instruction, there is a minimal amount of instructions, and a minimal amount
>of addressing modes.  More efficiency is obtained by working with the micro
>code because there are things that the macro instructions do in order to
>generalize the instructions for various purposes.  Micro code is to Macro
>code as assembler is to a high level language.  The Micro code provides more
>efficiency.
  Apart from the terminology.... what you just said is basically true, but the
following is .. erm... a little unjust to the CISC processors...

>Another Advantage of RISC is the abundance of Register memory.  CISC
>commonly contains few registers (The 68000 has 8 data registers and 8
>address registers) while RISC processors contain anywhere from 32 registers
>to a few hundred registers (It is not uncommon to have RISC processors that
>have 512 registers).  Since Register memory is about 10 times faster than
>main memory, most of the instructions are register to register, therefore
>increasing efficiency.
  The number of registers is basically up to the chip designer. While it isn't
uncommon to have many registers in a RISC chip, the same goes for most newer
CISC chips. Take, for example, the 80196KC et al.  (ok, granted it's a
microcontroller .. but who cares?). One of the reasons you don't get huge
register files in CISC chips these days is that most are enhancements on old
CISC chips that are 10+ years old.. back when the register file was a
ludicrous suggestion for a cheap processor. RISC is a fairly new technology,
and hence most RISC families started with register files.
  What I'm basically saying is that the RISC/CISC _architecture_ has nothing
to do with the size of the register file.

>In RISC chips the data path cycle time is minimized by logically reducing
>the number of steps it takes for an instruction to be executed and by
>physically shortening the distances between components in the chip (the
>large number of registers play a role in this).
  Bzzzt. Most speed-ups these days come from the material used. The newer
manufacturing technologies are major factors in speed-ups of current chips.
  Of course.. this only applies to the cycle time of _one_ instruction (and
in the i860 for example, it's 20ns). If the processor executes microcode, then
this will slow the processor down. Pipelining and parallel design (bit-parallel)
is being used to significantly reduce the microcode in current CISC processors.
Oh, I notice you mention this below..

>There is also a significant amount of parallellism and pipelining in RISC
>chips.  As soon as an instruction is started another instruction may be
>started even before the completion of the previous instruction.  Output of
>one instructions is passed on to another Unit in the chip for further
>processing while the current unit executing the instruction fetches a new
>instruction to process.  On many RISC chips as many as 4 instructions can be
>completed in one clock cylce as a result of this.
  This is true of most CISC chips these days (for example, the MC68040, which
has an average instruction cycle time of 2.5 clock ticks - don't quote me on
that though).

>>I was under the impression that CISC meant complicated instruction set
>>and RISC meant reduced instruction set. So wouldn't that mean larger
>>code size on a RISC machine compared to CISC.
>>What are the advantages of CISC and RISC?
>CISC I think is easier to program.  RISC is difficult as you have to worry
>about timing your instructions properly.  If you issued a memory write and
>do a read from the same location immediately after the write instruction,
>the data you may have wanted to read may not be there yet!  So you may have
>to issue the write a few steps earlier than you would normally on a CISC
>chip.
  Yes, CISC _is_ easier to program in most cases because the instructions are
generalized. As for memory writes.. if your chip is doing this then I suggest
you change manufacturers..
  The ONLY case of where data written may not be changed instantly is in
instruction caches, where a program self-modifies and the instruction cache is
not updated until the chache is flushed/refreshed.

>However, the CISC is slow compared to RISC.
  Only just.

    Richard.

ps. how do I know this? I have just completed the Digital Technology Bachelor
degree, and am moving on to Honours involved in advanced microprocessor design
coupled with advanced parallel microprocessor architectures.

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