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- Xref: sparky comp.sys.amiga.programmer:17468 comp.sys.amiga.hardware:21704
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- From: tbills@cse.unl.edu (Trent Bills)
- Newsgroups: comp.sys.amiga.programmer,comp.sys.amiga.hardware
- Subject: Re: CISC and RISC
- Date: 17 Dec 1992 14:43:33 GMT
- Organization: University of Nebraska--Lincoln
- Lines: 19
- Distribution: world
- Message-ID: <1gq3mlINNstt@crcnis1.unl.edu>
- References: <70436@cup.portal.com> <amipb.04wr@amipb.gna.org> <37844@cbmvax.commodore.com> <AHANSFOR.92Dec17000706@bigwpi.wpi.edu>
- NNTP-Posting-Host: cse.unl.edu
-
- In article <AHANSFOR.92Dec17000706@bigwpi.wpi.edu>, ahansfor@bigwpi.wpi.edu (Andrew L. Hansford) writes:
- |>
- |> 5) saving and restoring state on a page fault - Restarting an
- |> instruction and restoring the pipeline to its previous state (or near
- |> to it) can be very time consuming. (Of course pipelined CISC has the
- |> same problem)
- |>
-
- As far as I know, all of the current popular CISC chips ARE pipelined at
- least to some degree.
-
- The extreme cost of task switching is part of the motivation for putting
- multiple processors in one machine. Most (all?) workstation makers
- have some kind of multiprocessor machine.
-
- |> -- Andrew Hansford
- |> ahansfor@wpi.wpi.edu
-
- - Trent Bills
-