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- Path: sparky!uunet!uunet.ca!geac!zooid!tndb!jimomura
- From: jimomura@tndb.UUCP (Jim Omura)
- Newsgroups: comp.sys.amiga.hardware
- Subject: Re: WOC Toronto: Amiga's Future
- Distribution: world
- Message-ID: <jimomura.02ka@tndb.UUCP>
- References: <1992Dec16.054627.24848@spartan.ac.BrockU.CA>
- Date: 18 Dec 92 16:35:47 EST
- Organization: Not an Organization
- Lines: 56
-
- In article <1992Dec16.054627.24848@spartan.ac.BrockU.CA> tmc@spartan.ac.BrockU.CA (Tim Ciceran) writes:
- >In article <1992Dec15.173535.24953@oracle.us.oracle.com> dnavas@oracle.uucp
- >(David Navas) writes:
-
- ...
-
- [NOTE: I'm writing this WITHOUT reference notes so I may be wrong.
- Heck, even if I *had* my notes I could be wrong. -- Jim O. :-) ]
-
- >>Anyway, that's a 17ns pixel -- which is what we need for 1024x768x60, right?
-
- 17ns only affects horizontal resolution, not vertical. At least
- I can't see how it could affect vertical.
-
- >>Yeah, for free. This, along with the 100% backwards compatible makes it
- >>yet-again a 16bit blitter. Sigh....
-
- I think you've misunderstood the matter of "backward compatibility."
- My recollection is as follows: Mr. E. said specifically that there would
- be NO hardware backward compatibility from the future chipsets back
- to AGA or previous and AGA is not backward compatible with ECS and
- previous. That means clearly that they are not commited to make a
- "16 bit blitter". All they mean is that software that ran on the
- 16 bit blitter will still run (if at all feasible) on future chipsets.
- I'm fairly certain that he stated that the AGA blitter is 32 bit.
- That was partly how they got 4 times the throughput.
-
- ...
-
- [RE: parallel graphics processors]
-
- >>Like I really am going to believe this?
- >>Really, I'd prefer a wider CHIPbus.... What is more than one blitter going
- >>to do for me? I've only -got- one bloody bus (or do I?).
-
- You want this described from "what is a pixel level"? :-) The Amiga
- memory has contiguous memory bitplanes. To address a Pixel with 5 bits
- depth you have 5 areas of memory to address. Now, if you separate
- the graphics memory into 5 separate blocks of RAM, each with a
- processor, you can send the same instruction to the 5 processors
- at the same time, and they will all do the same thing at the same
- time in their respective memory areas. So if you want to move a
- row of pixels from the top of the screen, instead of a single processor
- copying a block if RAM from the "top" of the first page of RAM to the
- bottom of the first page of RAM, and then move on to the next page of
- RAM, each of the 5 processors (or whatever number of processors) move
- a block of RAM from the "top" of the screen to the bottom of the
- screen at the same time. In this case, you have speeded up a
- "block move" by 5 times.
-
- ...
-
- --
-
- Jim Omura, (416) 652-3880
- 'jimomura@lsuc'
-