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- Path: sparky!uunet!olivea!charnel!rat!usc!sdd.hp.com!cs.utexas.edu!torn!nott!bnrgate!bmerh85!bmerh85!hamish
- From: Hamish.Macdonald@x400gate.bnr.ca (Hamish Macdonald)
- Newsgroups: comp.sys.amiga.hardware
- Subject: Re: CISC and RISC
- Message-ID: <1992Dec16.185008.8536@bmerh85.bnr.ca>
- Date: 16 Dec 92 18:50:08 GMT
- References: <70436@cup.portal.com> <amipb.04wr@amipb.gna.org> <37844@cbmvax.commodore.com>
- <Bz8FD1.Dxt@ns1.nodak.edu> <1992Dec14.155039.7747@ugle.unit.no>
- <BzAxFw.Is6@dcs.ed.ac.uk> <BzBtx4.DLE@gpu.utcs.utoronto.ca>
- <71809@cup.portal.com>
- Sender: news@bmerh85.bnr.ca (Usenet News)
- Organization: Bell Northern Research
- Lines: 25
- In-Reply-To: Tony-Preston@cup.portal.com's message of Wed, 16 Dec 92 07:30:51 PST
-
- >>>>> On Wed, 16 Dec 92 07:30:51 PST,
- >>>>> In message <71809@cup.portal.com>,
- >>>>> Tony-Preston@cup.portal.com (ANTHONY FRANCIS PRESTON) wrote:
-
- ANTHONY> Believe the voice of experience, give me a CICS processor any
- ANTHONY> time! Besides, the 68040 has a 1.3 instruction/clock
- ANTHONY> execution rate, that is nearly as fast as most RISC machines.
-
- But can the 68040 be scaled up to 66-100 Mhz? The RISC designs can.
-
- ANTHONY> So what if the instructions execute three times faster if you
- ANTHONY> need almost twice as many! In a SPARC, I had 3 instructions
- ANTHONY> to load data from memory(two to build the address, one to
- ANTHONY> load relative to the address in a register), It sure executed
- ANTHONY> those instructions fast...
-
- But... Ideally you only have to build the address once, leave it in a
- register, and access all/most of your data (certainly any localized
- data) relative to that register. i.e. you rarely pay that 2
- instruction overhead.
-
- I will grant that:
- add.l dx,dy on the m680X0 (2 bytes)
- is shorter than:
- add dx,dy,dz on a RISC type (4 bytes, usually).
-