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Text File  |  1992-12-15  |  809 b   |  23 lines
  1. Newsgroups: comp.sys.acorn.tech
  2. From: steve@klaatu.demon.co.uk (Steve Loft)
  3. Path: sparky!uunet!pipex!demon!klaatu.demon.co.uk!steve
  4. Subject: ARM3 cache control in RISC OS 3.10
  5. Reply-To: steve@klaatu.demon.co.uk
  6. Distribution: world
  7. X-Mailer: cppnews $Revision: 1.20 $
  8. Organization: home
  9. Lines: 9
  10. Date: Tue, 15 Dec 1992 18:26:41 +0000
  11. Message-ID: <724469201snx@klaatu.demon.co.uk>
  12. Sender: usenet@demon.co.uk
  13.  
  14. Since RISC OS 3.10 has support for the ARM 3, I assume there are some
  15. SWI's for controlling the cache?  If so, could someone please post (or
  16. mail me) the details?
  17.  
  18. Steve
  19. -- 
  20. |  Steve Loft                                  steve@klaatu.demon.co.uk   |
  21. |  Doncaster,                                                             |
  22. |  South Yorks.                                                           |
  23.