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- Newsgroups: comp.lsi.cad,comp.arch
- Path: sparky!uunet!psinntp!xilinx!philip
- From: philip@xilinx.com (Philip Freidin)
- Subject: Re: Why no tri-state outputs in FPGA cells?
- Message-ID: <1992Dec17.170431.2520@xilinx.com>
- Sender: usenet@xilinx.com
- Organization: Xilinx Inc.
- References: <1992Dec14.221541.25270@dartvax.dartmouth.edu> <1992Dec15.010020.9274@super.org> <1992Dec15.193837.8890@dartvax.dartmouth.edu>
- Date: Thu, 17 Dec 1992 17:04:31 GMT
- Lines: 134
-
-
-
- In article <1992Dec14.221541.25270@dartvax.dartmouth.edu> pichet@coos.dartmouth.edu (Pichet Chintrakulchai) writes:
- >Hello,
- >
- >I've been working on a project designing a processor with FPGA's. One severe
- >limitation I found is that their cells do not have tri-state outputs and thus
- >forcing me to use MUXes on buses consuming a lot of the resources.
- >
- >Does anybody have any idea why they didn't make these cell outputs tri-state?
- >
- >Thanks.
- >Pichet Chintrakulchai (pichet@dartmouth.edu)
-
- Maybe you are using the wrong FPGAs :-)
-
- Enter advertising mode:
-
- One of the facilities of the Xilinx products that differentiates us
- from all the other lowly wanna-bees is that our XC3000 and XC4000
- products are full of tri-state buses. These are driven by what we
- call TBUFs, and there are 2 per logic block (i.e. just the right
- number). For each row of logic blocks, there are two rows of TBUFs
- with their associated horizontal long lines (the buses). On most of
- the larger chips, these long lines are split in the middle of the
- chip by splitters. For a given chip with N rows of logic blocks,
- you can have anywhere from N*2 bus lines (that span the width of
- the chip) to N*4 bus lines, in two groups of N*2, one for the left
- side of the chip, and one for the right. You can mix and match
- between half and full width within the one chip to get any number
- between N*2 and N*4.
-
- A sample of sizes follows:
-
- Part Numbers Full width buses Half width buses
-
- XC4005 28 56
- XC4006 32 64
- XC4008 36 72
- XC4010 40 80
- XC4013 48 96
-
- XC3090 40 80
- XC3190 40 80
- XC3195 44 88
-
- Exit advertising mode.
-
- With regard to building a processor, I have built (complete with front
- panel with flashing lights and toggle switches) a 20MIPS 16 bit RISC
- (native MIPS, not corelatable to anything else) with a XC4005 for the
- processor (used about 75% of the chip, the rest is available for
- peripheral intergration) and 6 XC3020 for the front pannel.
-
- If you want to talk to me about your project, (408)879-5180, or
- philip@xilinx.com
-
-
-
- In article <1992Dec15.193837.8890@dartvax.dartmouth.edu> eht@northstar.dartmouth.edu (Edward H. Truex) writes:
- >In article <1992Dec15.010020.9274@super.org> cfreese@super.org (Craig F. Reese) writes:
- >>
- >>You don't say which FPGA you are using but the Xilinx 4000 series does
- >>contain tristate buffers for just the kind of purpose you describe.
- >>The buffers are not on each CLB but adjacent. There are some
- >>limitations as to where the buffers can connect up. I have found
- >>designs where the functionallity did _not_ work for a given device (due
- >>to the size of the FPGA, size of my design, and the tristate buffer/bus
- >>resources) but a larger chip probably would have. In many other
- >>designs I have not used any tristate logic (so I'm glad the CLBs aren't
- >>all tristate by default).
- >
- >
- >I am working with Pichet (the originator of this thread) on a very
- >similar design, and I think his question can be rephrased. What we
- >are really trying to figure out is
- >
- >Is there an electrical reason why the short pieces of interconnect
- >(those that are connected through Xilinx's 'PIP's) cannot be tristated?
- >
- >The long lines obviuosly don't present any electrical problems as they
- >are simply edge to edge pieces of wire. Are the pass transistors in
- >the interconnect points the problem?
- >
- >Here's the motivation for our inquiries...
- >
- >With the current Xilinx parts (I am using XC4010's) the number of
- >busses that can be implemented is severely limited by the number
- >of long lines. In a design that requires many wide busses (I am
- >currently working on a 32 bit microprocessor) the number of long
- >lines available is not enough to implement a true bus structure.
- >As a result, I am forced to use a large number of fairly wide
- >multiplexers, and a correspondingly large number of CLBs and routing
- >resources. The ability to tristate the output of each CLB while
- >attaching it to a piece of "normal" routing would eliminate (or
- >reduce) bus constraints on chip, in addition to (possibly) freeing
- >up some of the CLBs that were previously used for bus redirection
- >to be used for "useful" logic.
- >
- >Thanks for any insights,
- >Tad Truex
-
-
- OK!!!!!!!!!! so you are using the RIGHT FPGAs!! :-)
-
- The reason that the local interconnect (short pieces of metal) dont have
- tristate capability in current families (we may in a future family) is
- for silicon real estate and speed reasons:
-
- (for those of you just reading along, PIPs are Programable Interconect
- Points, that link our chip routing resources together, either with
- buffers, pass transistors, or other techniques)
-
- 1) tristate-able pips would be much bigger, needing a control line, an
- input selector mux (for the tristate control line itself) and default
- logic for the non-tristate case. versus 1 pass transistor.
-
- 2) pips between local to long lines include a buffer, so bidirectionality
- would not work very well
-
- 3) tristateable pips are slower than direct pips
-
- 4) we like to guarantee valid signal levels on all interconnect, so
- we would have to include pull up resistors and 'weak keepers" everywhere
- as well. this would grow the chip size a lot.
-
- 5) assorted other reasons.
-
-
- --
- Philip Freidin: Product Planning Manager, Xilinx, INC
- (rest of clever .sig still under construction....
- coming to a terminal near you, Real Soon Now (tm))
-
-