NetNews Usenet Archive 1992 #30/NN_1992_30.iso/spool/comp/lsi/754

Internet Message Format | 1992-12-21 | 1.9 KB

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Subject: Jiggle chip tester
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Organization: Electrical Engineering, The University of Sydney, Australia
Date: Mon, 21 Dec 1992 02:47:08 GMT
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I recently posted this article to comp.arch.bus.vmebus in response to
someone's questions about a analogue/digital IO VME card. It occurred to
me that some readers of comp.lsi may also be interested.

The following blurb is a short description of the board. Please contact
me if anyone has any questions about it.

---------------------------------------------------------------

Jiggle is a general purpose chip tester which was designed specifically
for the training and testing of integrated circuits. It has been used
extensively to train VLSI implementations of low power artificial
neural network chips, although it could be used to test both digital and
analogue designs.

The Jiggle chip tester has the following features
- 64 digital IO channels
- 64 analogue IO channels
- 2 x 12 bit analogue to digital converters
  multiplexed to the 64 analogue input channels
- 64 x 12 bit digital to analogue converters
- All digital and analogue pins can be sampled simultaneously
  and read back at a later time
- Analogue inputs have high input impedance ($50 M\Omega$)
- Software configuration of analogue and digital IO direction
- Easily customisable via a chip interface board
- VME bus interface
- UNIX library for Jiggle IO


Regards,
Philip Leong.
--
Department of Electrical Engineering    Tel. [phone]
University of Sydney 2006        Fax. [phone]
Australia                Internet: [e-mail]