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- Path: sparky!uunet!zaphod.mps.ohio-state.edu!uwm.edu!linac!att!cbnewsc!cbfsb!att-out!oucsboss!oucsace!bobcat!fang
- From: fang@bobcat.ent.ohiou.edu ( Xuefeng Fang ECE )
- Newsgroups: comp.lang.vhdl
- Subject: help required
- Message-ID: <1992Dec12.210441.23631@oucsace.cs.ohiou.edu>
- Date: 12 Dec 92 21:04:41 GMT
- Sender: usenet@oucsace.cs.ohiou.edu (Network News Poster)
- Organization: College of Engg. & Tech., Ohio University, Athens, Ohio
- Lines: 10
- Originator: fang@bobcat.ent.ohiou.edu
-
- Hi, netters,
-
- I am a beginer for the VHDL. I am using the Valid VHDL package.
- After I finished analysis, I tried to make mg, however, I always
- got such message "too many ('s" and mg was failed. I realy have
- no idea what's wrong because I used the example given in the manual
- provided by Valid Inc. and followed excatly the instructions step
- by step.
- Would anyone please help me to figure out this problem?
- Thanks advanced.
-