NetNews Usenet Archive 1992 #30/NN_1992_30.iso/spool/comp/lang/verilog/478

Internet Message Format | 1992-12-20 | 796 b

Xref: sparky comp.lang.verilog:478 comp.lang.vhdl:601
Newsgroups: comp.lang.verilog,comp.lang.vhdl
Path: sparky!uunet!elroy.jpl.nasa.gov!dank
From: [e-mail] (Daniel R. Kegel)
Subject: Conversion of Verilog timing checks to VHDL?
Message-ID: <[e-mail]>
Sender: [e-mail] (Usenet)
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Organization: Image Analysis Systems Group, JPL
Date: Fri, 18 Dec 1992 04:36:18 GMT
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Hi all,
is there an accepted idiom for expressing the sort of timing checks
supported in Verilog, i.e.
    $width(negedge x, t0);
    $setup(x, posedge y, t0);
    $hold(posedge x, y, t0);
in VHDL?

I'm thinking about converting a PD program that generates Verilog
to also generate VHDL.
- Dan Kegel ([e-mail])