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- From: moss@cs.cmu.edu (Eliot Moss)
- Newsgroups: comp.arch
- Subject: paper available on Transactional Memory
- Message-ID: <MOSS.92Dec11173841@CRAFTY.cs.cmu.edu>
- Date: 11 Dec 92 22:38:41 GMT
- Article-I.D.: CRAFTY.MOSS.92Dec11173841
- Sender: news@cs.cmu.edu (Usenet News System)
- Reply-To: moss@cs.cmu.edu
- Distribution: comp
- Organization: Dept of Comp and Info Sci, Univ of Mass (Amherst)
- Lines: 25
- Nntp-Posting-Host: crafty.fox.cs.cmu.edu
-
- Recently Maurice Herlihy and I completed our technical report titled
- "Transactional Memory: Architectural Support for Lock-Free Data Structures".
- It describes a concept and implementation (ok, design) of means to accomplish
- essentially arbitrary multi-word atomic updates on shared memory
- multiprocessors. It piggybacks off any ownership-based cache coherency
- protocol and it eminently suitable for RISC design. (One way to think of it is
- as a logical way of extending Load-Linked / Store-Conditionally to multiple
- memory words.)
-
- You can obtain this report, which is official DEC CRL 92/07, via anonymous ftp
- from ibis.cs.umass.edu in pub/papers/crl-92-07.ps.Z (or omit the .Z if you
- want straight PostScript). The report includes a number of interesting
- simulation results for both a bus-based (snoopy) cache protocol and a
- directory based one. Maurice and I would be most interested in people's
- comments and reactions. Muarice can be reach via herlihy@crl.dec.com; I can be
- reached via moss@cs.umass.edu.
- --
-
- J. Eliot B. Moss, Associate Professor Visiting Associate Professor
- Department of Computer Science School of Computer Science
- Lederle Graduate Research Center Carnegie Mellon University
- University of Massachusetts 5000 Forbes Avenue
- Amherst, MA 01003 Pittsburgh, PA 15213-3891
- (413) 545-4206, 545-1249 (fax) (412) 268-6767, 681-5739 (fax)
- Moss@cs.umass.edu Moss@cs.cmu.edu
-