NetNews Usenet Archive 1992 #27/NN_1992_27.iso/spool/comp/unix/pcclone/32bit/492

Internet Message Format | 1992-11-20 | 3.8 KB

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From: [e-mail] (Larry Beaulieu)
Subject: Re: 486SXs as Unix Iron?
In-Reply-To: [e-mail]'s message of Tue, 17 Nov 1992 20:30:45 GMT
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In article <[e-mail]> [e-mail] (Todd Walk) writes:

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   Now the SX is less than 1/2 the size because of no math coprocessor.
   It's smaller yet because it uses a smaller line size, making it about
   a third the size of the DX.  So right off your yield/wafer has tripled.
   This allows you to sell the SX at about 1/2 the cost of the DX
   (packaging costs are constant, so you must charge more than 1/3 cost).


You are making a couple of assumptions which may not be valid.
Depending upon the differences in the line widths the 486SX would
require a more capable (i.e. more *expensive*) wafer stepper.  The additional
costs would be for capital outlay and also possibly for associated
maintenance costs.

If the 486 SX die were really that much smaller Intel probably designed their
masks to include multiple processors so as to maximize the number of die exposed per
step (as in wafer STEPPER, as in STEP and repeat).  One goal of wafer layout is
to minimize the number of steps in order to maximize throughput, which can be done
by maximizing the number of die exposed during each step.

   Now lets say there are 22 different DX sized areas that have faults
   that will ruin the chip that is there.  DX production has now dropped
   to 11/wafer (33%) and the SX production has dropped to 77/wafer (78%).
   Now you have 7 times as many SXs/wafer than DXs, allowing you to
   charge something like 1/5 the cost per chip.

A high percentage of faults in a production-worthy fab are due to alignment
errors of one sort or another.  This would mean that a fault would affect either
an entire die or the entire wafer.  Faults that would ruin only part of the
chip - such as those that would only ruin one die out of a multiple-die
exposure - would be identified and corrected very quickly.  Examples would be
a defective mask, dust, or any of various types of lens distortion.  Using
your analogy above (which would corrolate to 3 sx die per exposure), 22 defects
would work out to the same 33% yield.

The capital outlay required to produce chips of this complexity is *very* high.
You can bet that Intel expends considerable effort to ensure maximum throughput
and yield.  I would be surprised if the yield for either chip was under 90%.





--
Larry Beaulieu            [e-mail]
Bose Corporation        Phone: [phone] x6479
Framingham, MA 01701-9168    FAX:   [phone]

        All flames gleefully ignored.